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| General Features * Transmitter with Microcontroller Consisting of an AVR(R) Microcontroller and RF Transmitter PLL in a Single QFN24 5 mm x 5 mm Package (Pitch 0.65 mm) - f0 = 429 MHz to 439 MHz Temperature Range -40C to +85C Supply Voltage 2.0V to 4.0V Allowing Usage of Single Li-cell Power Supply Low Power Consumption - Active Mode: Typical 9.8 mA at 3.0V and 4 MHz Microcontroller-clock - Power-down Mode: Typical 200 nA at 3.0V Modulation Scheme ASK/FSK Integrated PLL Loop Filter Output Power of 7.5 dBm at 433.92 MHz Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply Single-ended Antenna Output with High Efficient Power Amplifier Very Robust ESD Protection: HBM 2500V, MM100V, CDM 1000V High Performance, Low Power AVR 8-bit Microcontroller, Similar to Popular ATtiny44 Well Known and Market-accepted RISC Architecture Non-volatile Program and Data Memories - 4 KBytes of In-system Programmable Program Memory Flash - 256 Bytes In-system Programmable EEPROM - 256 Bytes Internal SRAM Programming Lock for Self-programming Flash Program and EEPROM Data Security Peripheral Features - Two Timer/Counter, 8- and 16-bit Counters with Two PWM Channels on Both - 10-bit ADC - On-chip Analog Comparator - Programmable Watchdog Timer with Separate On-chip Oscillator - Universal Serial Interface (USI) Special Microcontroller Features - debugWIRE On-chip Debug System - In-system Programmable via SPI Port - External and Internal Interrupt Sources - Pin Change Interrupt on 12 Pins - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal Calibrated Oscillator - On-chip Temperature Sensor 12 Programmable I/O Lines * * * * * * * * * * * * Microcontroller with UHF ASK/FSK Transmitter ATA8742 * * * * 1. General Description The ATA8742 is a highly flexible programmable transmitter containing the AVR microcontroller ATtiny44V and the UHF PLL transmitters a small QFN24 5 mm x 5 mm package. This device is a member of a transmitter family covering several operating frequency ranges, which has been specifically developed for the demands of RF low-cost data transmission systems with data rates of up to 32 kBit/s. Its primary applications are in the areas of industrial/aftermarket Remote Keyless-Entry (RKE) systems, alarm, telemetering, energy metering systems, home automotion/entertainment and toys. The ATA8742 can be used in the frequency band of f0 = 433 MHz for ASK or FSK data transmission. 9151A-INDCO-07/09 Figure 1-1. ASK System Block Diagram UHF ASK/FSK Remote Control Transmitter ATA8742 S1 S1 S1 PXY PXY PXY PXY PXY PXY PXY ATtiny44V VDD GND PXY PXY PXY PXY PXY VS ATA8402 ATA8405 Power up/down ENABLE UHF ASK/FSK Remote Control Receiver ATA8202 ATA8204 Demod Control CLK f/4 PLL GND_RF 1 to 6 Microcontroller XTO VCO VCC_RF VS Antenna PLL XTO PA_ENABLE ANT2 Loop Antenna ANT1 PA LNA VCO VS 2 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 1-2. FSK System Block Diagram UHF ASK/FSK Remote Control Transmitter ATA8742 S1 S1 S1 PXY PXY PXY PXY PXY PXY PXY ATtiny44V VDD GND PXY PXY PXY PXY PXY VS ATA8402 ATA8405 Power up/down ENABLE UHF ASK/FSK Remote Control Receiver ATA8202 ATA8204 Demod Control CLK f/4 PLL GND_RF 1 to 6 Microcontroller XTO VCO VCC_RF VS Antenna PLL XTO PA_ENABLE ANT2 Loop Antenna ANT1 PA LNA VCO VS 3 9151A-INDCO-07/09 2. Pin Configuration Figure 2-1. Pinning QFN24 5 mm x 5 mm GND_RF ENABLE VS_RF XTAL 20 GND 24 23 22 21 VCC PB0 PB1 PB3/RESET PB2 PA7 1 2 3 4 5 6 7 8 9 10 11 19 18 17 16 15 14 13 12 GND PA0 PA1 PA2 PA3/T0 PA4/USCK PA5/MISO GND PA_ENABLE CLK ANT2 Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Description Symbol VCC PB0 PB1 PB3/RESET PB2 PA7 PA6 / MOSI CLK PA_ENABLE ANT2 ANT1 GND PA5/MISO PA4/SCK PA3/T0 PA2 PA1 PA0 GND XTAL VS_RF GND_RF ENABLE GND GND Function Microcontroller supply voltage Port B is a 4-bit bi-directional I/O port with internal pull-up resistor Port B is a 4-bit bi-directional I/O port with internal pull-up resistor Port B is a 4-bit bi-directional I/O port with internal pull-up resistor/reset input Port B is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Clock output signal for microcontroller. The clock output frequency is set by the crystal to fXTAL/4 Switches on power amplifier. Used for ASK modulation Emitter of antenna output stage Open collector antenna output Ground Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Microcontroller ground Connection for crystal Transmitter supply voltage Transmitter ground Enable input Ground Ground/backplane (exposed die pad) 4 ATA8742 9151A-INDCO-07/09 PA6/MOSI ANT1 ATA8742 2.1 Pin Configuration of RF Pins Pin Description Symbol Function Configuration VS Table 2-2. Pin 8 CLK Clock output signal for microconroller. The clock output frequency is set by the crystal to fXTAL/4. 100 CLK 100 PA_ENABLE 50 k UREF = 1.1V 9 PA_ENABLE Switches on power amplifier. Used for ASK modulation. 20 A ANT1 10 11 ANT2 ANT1 Emitter of antenna output stage. Open collector antenna output. ANT2 VS VS 1.5 k 1.2 k 20 XTAL Connection for crystal. XTAL 182 A 5 9151A-INDCO-07/09 Table 2-2. Pin 21 22 Pin Description (Continued) Symbol VS GND Function Supply voltage Ground Configuration See ESD protection circuitry (see Figure 8-1 on page 12). See ESD protection circuitry (see Figure 8-1 on page 12). ENABLE 200 k 23 ENABLE Enable input 6 ATA8742 9151A-INDCO-07/09 ATA8742 3. Functional Description For a typical application 3 to 4 interconnections between the AVR and the transmitter are required (see Figure 1-1 on page 2 and Figure 1-2 on page 3). The CLK line is used to allow the microcontroller to generate an XTAL-based transmitter signal. The ENABLE line is used to start the XTO, PLL, and clock output of the transmitter. The PA_ENABLE line is used to enable the power amplifier in ASK and FSK mode. In FSK mode a fourth line is necessary to modulate the load capacity of the XTAL. To wake up the system from standby mode at least one key input is required. After pressing the key, the microcontroller starts up with the internal RC oscillator. For TX operation user software must control ENABLE, PA_ENABLE, and XTAL load capacity as described in the following section. If ENABLE = L and PA_ENABLE = L the transmitter and the microcontroller (MCU) are in standby mode, reducing the power consumption so that a lithium cell can be used as power supply for several years. If ENABLE = H and PA_ENABLE = L, the XTO, PLL, and the CLK driver from the transmitter are activated. The crystal oscillator together with the PLL from the RF transmitter typically require < 1 ms until the PLL is locked and the clock output (Pin 8) is stable. If ENABLE = H and PA_ENABLE = H, the XTO, PLL, CLK driver, and the power amplifier (PA) are switched on. ASK modulation is achieved by switching on and off the power amplifier via PA_ENABLE. FSK modulation is achieved by switching on and off an additional capacitor between the XTAL load capacitor and GND, thus changing the reference frequency of the PLL. This is done using a MOS switch controlled by a microcontroller output. The power amplifier is switched on via PA_ENABLE = H. The MCU has to wait at least > 1 ms after setting ENABLE = H, before the external clock can be used. The external clock is connected via the timer0 input pin that clocks the USI from the MCU to achieve an accurate data transfer. The frequency of the internal RC oscillator is affected by ambient temperature and operating voltage. The USI provides two serial synchronous data transfer modes, with different physical I/O ports for the data output. The two wire mode is used for ASK and the three wire mode is used for FSK. If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount of current so that a lithium cell used as power supply can work for several years. With ENABLE = H the XTO, PLL, and the CLK driver are switched on. If PA_ENABLE remains L only the PLL and the XTO are running and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency. With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver, and the power amplifier are on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform the ASK modulation. 7 9151A-INDCO-07/09 3.1 Description of RF Transmitter The integrated PLL transmitter is particularly suitable for simple, low-cost RF applications. The VCO is locked to 32 fXTAL hence a 13.56 MHz crystal is needed for a 433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements. The crystal oscillator together with the PLL typically needs < 1 ms until the PLL is locked and the CLK output is stable. There is a wait time of 1 ms until the CLK is used for the microcontroller and the PA is switched on. The power amplifier is an open-collector output delivering a current pulse, which is nearly independent from the load impedance. Thus, the delivered output power is controllable via the connected load impedance. This output configuration enables simple matching to any kind of antenna or to 50. This results in a high power efficiency of = Pout/(IS,PA VS) of 36% for the power amplifier when an optimized load impedance of ZLoad = (166 + j223) is used at 3V supply voltage. 3.2 ASK Transmission The RF TX block is activated by ENABLE = H. PA_ENABLE must remain L for t 1 ms, then the CLK signal is taken to clock the AVR and the output power can be modulated by means of pin PA_ENABLE. After transmission, PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The RF TX is switched back to standby mode with ENABLE = L. 3.3 FSK Transmission The RF TX is activated by ENABLE = H. PA_ENABLE must remain L for t 1 ms, then the CLK signal is taken to clock the AVR and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The AVR starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference frequency of the PLL. When the switch is closed, the output frequency is lower than when the switch is open. After transmission, PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The RF TX is switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about 25% when the following tolerances are considered. Figure 3-1. Tolerances of Frequency Modulation VS CStray1 LM XTAL CM RS CStray2 C4 C0 Crystal equivalent circuit C5 CSwitch 8 ATA8742 9151A-INDCO-07/09 ATA8742 Using C4 = 9.2 pF 2%, C5 = 6.8 pF 5%, a switch port with CSwitch = 3 pF 10%, stray capacitances on each side of the crystal of CStray1 = CStray2 = 1 pF 10%, a parallel capacitance of the crystal of C0 = 3.2 pF 10% and a crystal with CM = 13 fF 10%, results in a typical FSK deviation of 21 kHz typical with worst case tolerances of 16.3 kHz to 28.8 kHz. 3.4 CLK Output An output CLK signal is provided for the integrated AVR. The delivered signal is CMOS compatible if the load capacitance is lower than 10 pF. 3.4.1 Clock Pulse Take-over The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel(R)'s AVR microcontroller starts with an integrated RC-oscillator to switch on the RF TX with ENABLE = H, and after 1 ms assumes the clock signal of the transmission IC, so that the message can be sent with crystal accuracy. Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad,opt = (166 + j223). There must be a low resistive path to VS to deliver the DC current. The delivered current pulse of the power amplifier is 9 mA and the maximum output power is delivered to a resistive load of 465 if the 1.0 pF output capacitance of the power amplifier is compensated by the load impedance. An optimum load impedance of: ZLoad = 465 || j/(2 x 1.0 pF) = (166 + j223) is achieved for the maximum output power of 7.5 dBm. The load impedance is defined as the impedance seen from the RF TX's ANT1, ANT2 into the matching network. This large signal load impedance should not be confused with the small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier. Less output power is achieved by lowering the real parallel part of 465 where the parallel imaginary part should be kept constant. Output power measurement can be done using the circuit shown in Figure 8-4 on page 16. Note that the component values must be changed to compensate the individual board parasitics until the RF TX has the right load impedance ZLoad,opt = (166 + j223). In addition, the damping of the cable used to measure the output power must be calibrated out. 3.4.2 4. Microcontroller Block More detailed information about the microcontroller block can be found in the appendix. 9 9151A-INDCO-07/09 5. Absolute Maximum Ratings Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Input voltage Note: Symbol VS Ptot Tj Tstg Tamb VmaxPA_ENABLE -55 -55 -0.3 Minimum Maximum 5 100 150 125 125 (VS + 0.3) (1) Unit V mW C C C V 1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V. 6. Thermal Resistance Parameters Junction ambient Symbol RthJA Value 170 Unit K/W 7. Electrical Characteristics VS = 2.0V to 4.0V, Tamb = 25C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25C. All parameters are referred to GND (pin 7). Parameters Supply current Supply current Output power Output power variation for the full temperature range Test Conditions Power down, microcontroller Watchdog timer disabled Power up, 4 MHz internal RC oscillator VS = 3.0V, Tamb = 25C, f = 433.92 MHz, ZLoad = (166 + j233) Tamb = 25C, VS = 3.0V VS = 2.0V Tamb = 25C, VS = 3.0V VS = 2.0V POut = PRef + PRef Selectable by load impedance fCLK = f0/128 Load capacitance at pin CLK = 10 pF fO 1 x fCLK fO 4 x fCLK other spurious are lower fXTO = f0/32 fXTAL = resonant frequency of the XTAL, CM 10 fF, load capacitance selected accordingly Tamb = 25C Symbol IS_Off IS_Transmit PRef PRef PRef PRef PRef POut_typ 0 5.5 Min. Typ. 210 24.35 9.8 7.5 10 Max. Unit nA A mA dBm -1.5 -4.0 -2.0 -4.5 7.5 dB dB dB dB dBm Output power variation for the full temperature range Achievable output-power range Spurious emission -55 -52 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO -30 fXTAL 250 +30 ppm kHz PLL loop bandwidth Note: 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V. 10 ATA8742 9151A-INDCO-07/09 ATA8742 7. Electrical Characteristics (Continued) VS = 2.0V to 4.0V, Tamb = 25C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25C. All parameters are referred to GND (pin 7). Parameters Phase noise of phase comparator In-loop phase noise PLL Phase noise VCO Frequency range of VCO Clock output frequency (CMOS microcontroller compatible) Voltage swing at pin CLK Series resonance R of the crystal Capacitive load at pin XT0 FSK modulation frequency rate ASK modulation frequency rate ENABLE input Duty cycle of the modulation signal = 50% Duty cycle of the modulation signal = 50% Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high VIl VIh IIn VIl VIh IIn 0 0 1.7 20 1.7 0.25 VS(1) 5 CLoad 10 pF V0h V0l Rs VS x 0.8 Test Conditions Referred to fPC = fXT0, 25 kHz distance to carrier 25 kHz distance to carrier at 1 MHz at 36 MHz fVCO 429 f0/128 VS x 0.2 110 7 32 32 0.25 Symbol Min. Typ. -116 -86 -94 -125 Max. -110 -80 -90 -121 439 Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz MHz V V pF kHz kHz V V A V V A PA_ENABLE input Note: 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V. 11 9151A-INDCO-07/09 8. Application For the supply-voltage blocking capacitor C3, a value of 68 nF/X7R is recommended. C1 and C2 are used to match the loop antenna to the power amplifier, where C1 typically is 8.2 pF/NP0 and C2 is 6 pF/NP0 (10 pF + 15 pF in series); for C2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility of realizing the ZLoad,opt by using standard valued capacitors. Together with the pins and the PCB board wires C1 forms a series resonance loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 (50 nH to 100 nH) can be printed on PCB. C4 should be selected that the XTO runs on the load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF load-capacitance crystal. Figure 8-1. VS ESD Protection Circuit ANT1 CLK PA_ENABLE ANT2 XTAL ENABLE GND 12 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 8-2. Typical ASK Application ATA8742 VCC C5 C8 Q1 VCC 24 GND 23 ENABLE 22 GND_RF 21 VCC_RF 20 XTAL 19 GND SW1 18 PA0 17 1 VDD C7 R3 C6 2 PB0/XTAL1 3 PB1/XTAL2 4 PB3/RESET 5 PB2 6 PA6 ADC6 CLK PA7 ADC7 PA_ENABLE PA4/SCK PA2 PA1 SW2 16 SW3 ATA874x PA3/T0 15 14 13 PA5/MISO ANT2 ANT1 11 R2 7 8 9 10 12 GND R4 R1 L1 C1 VCC L2 C2 C3 C4 Table 8-1. Component Bill of Material Value 315 MHz 433.92 MHz 82 nH 27 nH 1 nF 2.7 pF 16 pF 1.6 pF 68 nF 100 nF 868.3 MHz 22 nH 2.2 nH 1 nF 1.5 pF 4.3 pF 0.3 pF 68 nF 100nF LL1608-FSL/ TOKO LL1608-FSL/ TOKO GRM1885C/ Murata GRM1885C/ Murata GRM1885C/ Murata GRM1885C/ Murata This cap must be placed as close as possible to the pin Ant1 and Ant2 On the demo board 2 capacitors in series are used to reduce the tolerance On the demo board 2 capacitors in series are used to reduce the tolerance Type/ Manufacturer Note L1 L2 C1 C2 C3 C4 C5 C6 100 nH 39 nH 1 nF 3.9 pF 27 pF 3.9 pF 68 nF 100 nF GRM188R71C/ This cap must placed as close as possible to the Murata VCC_RF GRM188R71C / This cap must placed as close as possible to the Murata VDD 13 9151A-INDCO-07/09 Table 8-1. Component C7 C8 Q1 R1 R2 R3 R4 Bill of Material (Continued) Value 100 nF 10 pF 9.843750 MHz 100 k 100 k 10 k 1.8 k 100 nF 12 pF 13.56 MHz 100 k 100 k 10 k 1.8 k 100 nF 12 pF 13.567187 MHz 100 k 100 k 10 k 1.8 k This resistor can be resigned if the ASK modulation is performed using PA5 (MISO). Type/ Manufacturer Note GRM188R71C / Murata GRM1885C/ Murata DSX530GK/ KDS Figure 8-3. Typical FSK Application ATA8742 VCC C5 C8 T1 Q1 21 VCC_RF 20 XTAL 19 GND C9 VCC 24 GND 23 ENABLE 22 GND_RF SW1 18 PA0 17 1 VDD 2 C7 R3 C6 SW2 PB0/XTAL1 3 PB1/XTAL2 4 PB3/RESET 5 PB2 6 PA6 ADC6 CLK PA7 ADC7 PA_ENABLE PA1 16 PA2 SW3 ATA874x PA3/T0 15 14 PA4/SCK 13 PA5/MISO ANT2 ANT1 11 R2 7 8 9 10 12 GND C1 VCC R1 L1 L2 C2 C3 C4 Note: FSK Modulation is achieved by switching on and off an additional capacitor between the XTAL load capacitor and GND. This is done using a MOS switch controlled by a microcontroller output. 14 ATA8742 9151A-INDCO-07/09 ATA8742 Table 8-2. Component 315 MHz L1 L2 C1 C2 C3 C4 C5 C6 C7 C8 C9 T1 Q1 R1 R2 R3 R4 9.843750 MHz 100 k 100 k 10 k 1.8 k 13.56 MHz 100 k 100 k 10 k 1.8 k 13.567187 MHz 100 k 100 k 10 k 1.8 k 100 nH 39 nH 1 nF 3.9 pF 27 pF 3.9 pF 68 nF 100 nF 100 nF 3.9 pF 18 pF Bill of Material Value 433.92 MHz 82 nH 27 nH 1 nF 2.7 pF 16 pF 1.6 pF 68 nF 100 nF 100 nF 4.7 pF 8.2 pF 868.3 MHz 22 nH 2.2 nH 1 nF 1.5 pF 4.3 pF 0.3 pF 68 nF 100nF 100 nF 5.6 pF 5.6 pF LL1608-FSL/ TOKO LL1608-FSL/ TOKO GRM1885C/ Murata GRM1885C/ Murata GRM1885C/ Murata GRM1885C/ Murata This cap must be placed as close as possible to the pin Ant1 and Ant2 On the demo board 2 capacitors in series are used to reduce the tolerance On the demo board 2 capacitors in series are used to reduce the tolerance Type/ Manufacturer Note GRM188R71C/ This cap must placed as close as possible to the Murata VCC_RF GRM188R71C / This cap must placed as close as possible to the Murata VDD GRM188R71C / Murata GRM1885C/ Murata GRM1885C/ Murata BSS83 DSX530GK/ KDS Frequency deviation of 16 kHz will be performed using the combination of C8 and C9 Frequency deviation of 16 kHz will be performed using the combination of C8 and C9 15 9151A-INDCO-07/09 Table 8-3. Transmitter Pin Cross Reference List Pin Name CLK Pin Number ATA8401/02/03 1 2 3 4 5 6 7 8 Pin Number ATA8741/42/43 8 9 10 11 20 21 22 23 PA_ENABLE ANT2 ANT1 XTAL VS GND ENABLE Note: For the ATA8742, the following points differs from the datasheets: - The temperature range is limited to -40C to +85C - ESD protection: HBM 2500V, MM 100V, CDM 1000V - Figure 8-4 on page 16: Two output power measurement - For FSK modulation, an additional MOS switch is required Figure 8-4. Output Power Measurement ATA8742 VS C1 = 1 nF L1 = 33 nH ANT1 ZLopt ANT2 C2 = 2.4 pF Z = 50 Rin 50 Power meter 16 ATA8742 9151A-INDCO-07/09 ATA8742 Table 8-4. Microcontroller Cross Reference List Pin Name VCC PB0 PB1 PB3/NRESET PB2 PA7 PA6/MOSI PA5/MISO PA4/USCK PA3/T0 PA2 PA1 PA0 GND Note: Pin Number ATtiny44V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Number ATA8741/ATA8742/ATA8743 1 2 3 4 5 6 7 13 14 15 16 17 18 19 For the ATA8741/ATA8742/ATA8743, the following points differs from the ATtiny44V datasheet: - The temperature range is limited to -40C to +85C - The supply voltage range is limited from 2.0V to 4.0V 17 9151A-INDCO-07/09 Appendix: Microcontroller ATtiny24/44/84 18 ATA8742 9151A-INDCO-07/09 ATA8742 9. Overview The ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 9.1 Block Diagram Figure 9-1. VCC 8-BIT DATABUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER Block Diagram INTERNAL CALIBRATED OSCILLATOR WATCHDOG TIMER MCU CONTROL REGISTER TIMING AND CONTROL PROGRAM FLASH SRAM INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z MCU STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1 INSTRUCTION DECODER CONTROL LINES ALU STATUS REGISTER INTERRUPT UNIT PROGRAMMING LOGIC ISP INTERFACE EEPROM OSCILLATORS ANALOG COMPARATOR DATA REGISTER PORT A DATA DIR. REG.PORT A ADC DATA REGISTER PORT B DATA DIR. REG.PORT B + - PORT A DRIVERS PORT B DRIVERS PA7-PA0 PB3-PB0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting 19 9151A-INDCO-07/09 architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny24/44/84 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 9.2 Automotive Quality Grade The ATtiny24/44/84 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949 grade 1. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATtiny24/44/84 have been verified during regular product qualification as per AEC-Q100. As indicated in the ordering information paragraph, the product is available in only one temperature grade, Table 9-1. Temperature -40; +125 Temperature Grade Identification for Automotive Products Temperature Identifier Z Comments Full Automotive Temperature Range 20 ATA8742 9151A-INDCO-07/09 ATA8742 9.3 9.3.1 Pin Descriptions VCC Supply voltage. 9.3.2 GND Ground. 9.3.3 Port B (PB3...PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (`0') RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny24/44/84 as listed on Section 19.3 "Alternate Port Functions" on page 77. 9.3.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Figure 16-1 on page 56. Shorter pulses are not guaranteed to generate a reset. 9.3.5 Port A (PA7...PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in "Alternate Port Functions" on page 77 21 9151A-INDCO-07/09 10. Resources A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr. 11. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 22 ATA8742 9151A-INDCO-07/09 ATA8742 12. CPU Core 12.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 12.2 Architectural Overview Figure 12-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control Instruction Register 32 x 8 General Purpose Registrers Interrupt Unit Watchdog Timer Indirect Addressing Instruction Decoder Direct Addressing ALU Control Lines Analog Comparator Timer/Counter 0 Data SRAM Timer/Counter 1 Universal Serial Interface EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. 23 9151A-INDCO-07/09 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 12.3 ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description. 12.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 24 ATA8742 9151A-INDCO-07/09 ATA8742 12.4.1 SREG - AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG * Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the "Instruction Set Description" for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. 25 9151A-INDCO-07/09 12.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * One 8-bit output operand and one 8-bit result input * Two 8-bit output operands and one 8-bit result input * Two 8-bit output operands and one 16-bit result input * One 16-bit output operand and one 16-bit result input Figure 12-2 on page 26 shows the structure of the 32 general purpose working registers in the CPU. Figure 12-2. AVR CPU General Purpose Working Registers 7 R0 R1 R2 ... R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02 Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 12-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 12.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 12-3 on page 27. 26 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 12-3. The X-, Y-, and Z-registers 15 X-register 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0 15 Y-register 7 R29 (0x1D) 15 Z-register 7 R31 (0x1F) YH 0 7 R28 (0x1C) ZH 0 7 R30 (0x1E) YL 0 0 ZL 0 0 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 12.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 12.6.1 SPH and SPL - Stack Pointer High and Low Bit 0x3E (0x5E) 0x3D (0x5D) 15 SP15 SP7 7 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL Read/Write R/W R/W Initial Value 0 0 27 9151A-INDCO-07/09 12.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 12-4 on page 28 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 12-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 12-5 on page 28 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 12-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 12.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on page 66. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. 28 ATA8742 9151A-INDCO-07/09 ATA8742 When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; start EEPROM write ; disable interrupts during timed sequence C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< 9151A-INDCO-07/09 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 12.8.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 30 ATA8742 9151A-INDCO-07/09 ATA8742 13. Memories This section describes the different memories in the ATtiny24/44/84. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny24/44/84 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 13.1 In-System Re-programmable Flash Program Memory The ATtiny24/44/84 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 1024/2048/4096 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny24/44/84 Program Counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program memory locations. "Memory Programming" on page 180 contains a detailed description on Flash data serial downloading using the SPI pins. Constant tables can be allocated within the entire Program memory address space (see the LPM - Load Program memory instruction description). Timing diagrams for instruction fetch and execution are presented in "Instruction Execution Timing" on page 28. Figure 13-1. Program Memory Map Program Memory 0x0000 0x03FF/0x07FF/0xFFF 13.2 SRAM Data Memory Figure 13-2 on page 32 shows how the ATtiny24/44/84 SRAM Memory is organized. The lower 160 Data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O memory, and the last 128/256/512 locations address the internal data SRAM. The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. 31 9151A-INDCO-07/09 When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny24/44/84 are all accessible through all these addressing modes. The Register File is described in "General Purpose Register File" on page 26. Figure 13-2. Data Memory Map Data Memory 32 Registers 64 I/O Registers 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 Internal SRAM (128/256/512 x 8) 0x0DF/0x015F/0x025F 13.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 13-3 on page 32. Figure 13-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Data WR Data RD Compute Address Address valid Memory Access Instruction Next Instruction 32 ATA8742 9151A-INDCO-07/09 Read Write ATA8742 13.3 EEPROM Data Memory The ATtiny24/44/84 contains 128/256/512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see "Serial Downloading" on page 184. 13.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 13-1 on page 39. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See "Preventing EEPROM Corruption" on page 36 for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. See "Atomic Byte Programming" on page 33 and "Split Byte Programming" on page 33 for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 13.3.2 Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEARL Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 1. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations. 13.3.3 Split Byte Programming It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after Power-up). 13.3.4 Erase To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 1). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations. 33 9151A-INDCO-07/09 13.3.5 Write To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 1). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations. The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in "Oscillator Calibration Register - OSCCAL" on page 48. The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. 34 ATA8742 9151A-INDCO-07/09 ATA8742 Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode ldi out r16, (0< C Code Example void EEPROM_write(unsigned char ucAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1< 9151A-INDCO-07/09 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r17) in address register out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in ret r16,EEDR C Code Example unsigned char EEPROM_read(unsigned char ucAddress) { /* Wait for completion of previous write */ while(EECR & (1< Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 36 ATA8742 9151A-INDCO-07/09 ATA8742 13.4 I/O Memory The I/O space definition of the ATtiny24/44/84 is shown in "Register Summary" on page 228. All ATtiny24/44/84 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. See the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and Peripherals Control Registers are explained in later sections. 13.4.1 General Purpose I/O Registers The ATtiny24/44/84 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 37 9151A-INDCO-07/09 13.5 13.5.1 Register Description EEARH - EEPROM Address Register Bit 0x1F (0x3F) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 EEAR8 R/W X EEARH * Bits 7..1 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bit 0 - EEAR8: EEPROM Address The EEPROM Address Register - EEARH - specifies the most significant bit for EEPROM address in the 512 bytes EEPROM space for Tiny84. This bit is reserved bit in the ATtiny24/44 and will always read as zero. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 13.5.2 EEARL - EEPROM Address Register Bit 0x1E (0x3E) Read/Write Initial Value 7 EEAR7 R/W X 6 EEAR6 R/W X 5 EEAR5 R/W X 4 EEAR4 R/W X 3 EEAR3 R/W X 2 EEAR2 R/W X 1 EEAR1 R/W X 0 EEAR0 R/W X EEARL * Bits 7..0 - EEAR7..0: EEPROM Address The EEPROM Address Register - EEARL - specifies the EEPROM address. In the 128 bytes EEPROM space in ATiny24 bit 7 is reserved and always read as zero. The EEPROM data bytes are addressed linearly between 0 and 128/256/512. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 13.5.3 EEDR - EEPROM Data Register Bit 0x1D (0x3D) Read/Write Initial Value 7 EEDR7 R/W 0 6 EEDR6 R/W 0 5 EEDR5 R/W 0 4 EEDR4 R/W 0 3 EEDR3 R/W 0 2 EEDR2 R/W 0 1 EEDR1 R/W 0 0 EEDR0 R/W 0 EEDR * Bits 7..0 - EEDR7..0: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 13.5.4 EECR - EEPROM Control Register Bit 0x1C (0x3C) Read/Write Initial Value 7 - R 0 6 - R 0 5 EEPM1 R/W X 4 EEPM0 R/W X 3 EERIE R/W 0 2 EEMPE R/W 0 1 EEPE R/W X 0 EERE R/W 0 EECR 38 ATA8742 9151A-INDCO-07/09 ATA8742 * Bit 7 - Res: Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny24/44/84. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit. * Bit 6 - Res: Reserved Bit This bit is reserved in the ATtiny24/44/84 and will always read as zero. * Bits 5, 4 - EEPM1 and EEPM0: EEPROM Mode Bits The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 13-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 13-1. EEPM1 0 0 1 1 EEPROM Mode Bits EEPM0 0 1 0 1 Programming Time 3.4 ms 1.8 ms 1.8 ms - Operation Erase and Write in one operation (Atomic Operation) Erase Only Write Only Reserved for future use * Bit 3 - EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming. * Bit 2 - EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. * Bit 1 - EEPE: EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal - EERE - is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the 39 9151A-INDCO-07/09 EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. 13.5.5 GPIOR2 - General Purpose I/O Register 2 Bit 0x15 (0x35) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 GPIOR2 13.5.6 GPIOR1 - General Purpose I/O Register 1 Bit 0x14 (0x34) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 GPIOR1 13.5.7 GPIOR0 - General Purpose I/O Register 0 Bit 0x13 (0x33) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 GPIOR0 40 ATA8742 9151A-INDCO-07/09 ATA8742 14. System Clock and Clock Options 14.1 Clock Systems and their Distribution Figure 14-1 on page 41 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in "Power Management and Sleep Modes" on page 50. The clock systems are detailed below. Figure 14-1. Clock Distribution ADC General I/O Modules CPU Core RAM Flash and EEPROM clkI/O clkADC AVR Clock Control Unit clkCPU clkFLASH Reset Logic Source clock Watchdog Timer Watchdog clock System Clock Prescaler Clock Multiplexer Watchdog Oscillator External Clock Calibrated RC Crystal Oscillator Oscillator Low-Frequency Crystal Oscillator Calibrated RC Oscillator 14.1.1 CPU Clock - clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 14.1.2 I/O Clock - clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. 14.1.3 Flash Clock - clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 14.1.4 ADC Clock - clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 41 9151A-INDCO-07/09 14.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 14-1. Device Clocking Options Select(1) CKSEL3.0 0000 0010 0100 0110 1000-1111 0101, 0111, 0011,0001 Device Clocking Option External Clock Calibrated Internal RC Oscillator 8.0 MHz Watchdog Oscillator 128 kHz External Low-frequency Oscillator External Crystal/Ceramic Resonator Reserved Note: 1. For all fuses "1" means unprogrammed while "0" means programmed. The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 14-2 on page 42. Table 14-2. Number of Watchdog Oscillator Cycles Typ Time-out 4 ms 64 ms Number of Cycles 512 8K (8,192) 14.3 Default Clock Source The device is shipped with CKSEL = "0010", SUT = "10", and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at 8.0 MHz with longest start-up time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer. 14.4 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 14-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 14-3 on page 43. For ceramic resonators, the capacitor values given by the manufacturer should be used. 42 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 14-2. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 14-3 on page 43. Table 14-3. CKSEL3..1 100(1) 101 110 111 Notes: Crystal Oscillator Operating Modes Frequency Range (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) - 12 - 22 12 - 22 12 - 22 1. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 14-4 on page 44. 43 9151A-INDCO-07/09 Table 14-4. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK(1) 258 CK(1) 1K CK(2) 1K CK(2) 1K CK(2) 16K CK 16K CK 16K CK Additional Delay from Reset (VCC = 5.0V) 14CK + 4.1 ms 14CK + 65 ms 14CK 14CK + 4.1 ms 14CK + 65 ms 14CK 14CK + 4.1 ms 14CK + 65 ms CKSEL0 0 0 0 0 1 1 1 1 Notes: SUT1..0 00 01 10 11 00 01 10 11 Recommended Usage Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. 14.5 Low-frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL fuses to `0110'. The crystal should be connected as shown in Figure 14-2. See the 32 kHz Crystal Oscillator Application Note for details on oscillator operation and how to choose appropriate values for C1 and C2. When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 14-5. Table 14-5. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection Start-up Time from Power Down and Power Save 1K CK(1) 1K CK(1) 32K CK Additional Delay from Reset (VCC = 5.0V) 4 ms 64 ms 64 ms Reserved 1. These options should only be used if frequency stability at start-up is not important for the application. SUT1..0 00 01 10 11 Notes: Recommended usage Fast rising power or BOD enabled Slowly rising power Stable frequency at start-up 44 ATA8742 9151A-INDCO-07/09 ATA8742 14.6 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 29-2 on page 197 and "Internal Oscillator Speed" on page 221 for more details. The device is shipped with the CKDIV8 Fuse programmed. See "System Clock Prescaler" on page 47 for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 14-6. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 29-2 on page 197. By changing the OSCCAL register from SW, see "Oscillator Calibration Register - OSCCAL" on page 48, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 29-2 on page 197. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section "Calibration Byte" on page 182. Table 14-6. Internal Calibrated RC Oscillator Operating Modes CKSEL3..0 0010 Note: (1) Nominal Frequency 8.0 MHz 1. The device is shipped with this option selected. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 14-7 on page 45.. Table 14-7. SUT1..0 00 01 10(1) 11 Note: Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power-down 6 CK 6 CK 6 CK Additional Delay from Reset (VCC = 5.0V) 14CK 14CK + 4 ms 14CK + 64 ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power 1. The device is shipped with this option selected. 14.7 External Clock To drive the device from an external clock source, CLKI should be driven as shown in Figure 14-3 on page 46. To run the device on an external clock, the CKSEL Fuses must be programmed to "0000". 45 9151A-INDCO-07/09 Figure 14-3. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL CLKI GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 14-8 on page 46. Table 14-8. SUT1..0 00 01 10 11 Start-up Times for the External Clock Selection Start-up Time from Power-down and Power-save 6 CK 6 CK 6 CK Additional Delay from Reset 14CK 14CK + 4 ms 14CK + 64 ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. See to "System Clock Prescaler" on page 47 for details. 46 ATA8742 9151A-INDCO-07/09 ATA8742 14.8 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25C. This clock may be select as the system clock by programming the CKSEL Fuses to "0100". When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 14-9 on page 47. Table 14-9. SUT1..0 00 01 10 11 Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Power-down and Power-save 6 CK 6 CK 6 CK Additional Delay from Reset 14CK 14CK + 4 ms 14CK + 64 ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power 14.9 System Clock Prescaler The ATtiny24/44/84 system clock can be divided by setting the Clock Prescale Register - CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 14-10 on page 49. 14.9.1 Switching Time When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. 47 9151A-INDCO-07/09 14.10 Register Description 14.10.1 Oscillator Calibration Register - OSCCAL Bit 0x31 (0x51) Read/Write Initial Value 7 CAL7 R/W 6 CAL6 R/W 5 CAL5 R/W 4 CAL4 R/W 3 CAL3 R/W 2 CAL2 R/W 1 CAL1 R/W 0 CAL0 R/W OSCCAL Device Specific Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in Table 29-2 on page 197. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 29-2 on page 197. Calibration outside that range is not guaranteed. Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail. The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80. The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. 14.10.2 Clock Prescale Register - CLKPR Bit 0x26 (0x46) Read/Write Initial Value 7 CLKPCE 6 - 5 - 4 - 3 CLKPS3 2 CLKPS2 1 CLKPS1 0 CLKPS0 CLKPR R/W 0 R 0 R 0 R 0 R/W R/W R/W R/W See Bit Description * Bit 7 - CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. * Bits 6..4 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bits 3..0 - CLKPS3..0: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 14-10 on page 49. 48 ATA8742 9151A-INDCO-07/09 ATA8742 To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to "0000". If CKDIV8 is programmed, CLKPS bits are reset to "0011", giving a division factor of eight at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 14-10. Clock Prescaler Select CLKPS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CLKPS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CLKPS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CLKPS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock Division Factor 1 2 4 8 16 32 64 128 256 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 49 9151A-INDCO-07/09 15. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application's requirements. 15.1 Sleep Modes Figure 14-1 on page 41 presents the different clock systems in the ATtiny24/44/84, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 15-1 shows the different sleep modes and their wake up sources Table 15-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains Oscillators Main Clock Source Enabled Wake-up Sources INT0 and Pin Change Sleep Mode Idle ADC Noise Reduction Power-down Stand-by Note: (2) X X X X X X X(1) X(1) X X X X X X X (1) 1. For INT0, only level interrupt. 2. Only recommended with external crystal or resonator selected as clock source To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Standby or Power-down) will be activated by the SLEEP instruction. See Table 15-2 on page 53 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 15.2 Idle Mode When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, 50 ATA8742 9151A-INDCO-07/09 Watchdog Interrupt X X X SPM/ EEPROM Ready Other I/O clkFLASH clkCPU clkADC ADC clkIO ATA8742 the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register - ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 15.3 ADC Noise Reduction Mode When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode. 15.4 Power-down Mode When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. See "External Interrupts" on page 68 for details 15.5 Standby Mode When the SM1..0 bits are 11 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. 15.6 Power Reduction Register The Power Reduction Register (PRR), see "PRR - Power Reduction Register" on page 54, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See "Power-down Supply Current" on page 212 for examples. In all other sleep modes, the clock is already stopped. 51 9151A-INDCO-07/09 15.7 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device's functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 15.7.1 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. See "Analog to Digital Converter" on page 154 for details on ADC operation. 15.7.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. See "Analog Comparator" on page 150 for details on how to configure the Analog Comparator. 15.7.3 Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. See "Brown-out Detection" on page 59 for details on how to configure the Brown-out Detector. 15.7.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. See "Internal Voltage Reference" on page 60 for details on the start-up time. 15.7.5 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. See "Watchdog Timer" on page 60 for details on how to configure the Watchdog Timer. 15.7.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In 52 ATA8742 9151A-INDCO-07/09 ATA8742 some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. See the section "Digital Input Enable and Sleep Modes" on page 76 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). See "DIDR0 - Digital Input Disable Register 0" on page 172 for details. 15.8 15.8.1 Register Description MCUCR - MCU Control Register The MCU Control Register contains control bits for power management. Bit 7 - Read/Write Initial Value R 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 -- R 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bit 5 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer's purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. * Bits 4, 3 - SM1..0: Sleep Mode Select Bits 2..0 These bits select between the three available sleep modes as shown in Table 15-2 on page 53. Table 15-2. SM1 0 0 1 1 Note: Sleep Mode Select SM0 0 1 0 1 Sleep Mode Idle ADC Noise Reduction Power-down Standby(1) 1. Only recommended with external crystal or resonator selected as clock source * Bit 2 - Res: Reserved Bit This bit is a reserved bit in the ATtiny24/44/84 and will always read as zero. 53 9151A-INDCO-07/09 15.8.2 PRR - Power Reduction Register Bit 7 - 6 - R 0 5 - R 0 4 - R 0 3 PRTIM1 R/W 0 2 PRTIM0 R/W 0 1 PRUSI R/W 0 0 PRADC R/W 0 PRR Read/Write Initial Value R 0 * Bits 7, 6, 5, 4- Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bit 3- PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. * Bit 2- PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. * Bit 1 - PRUSI: Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation. * Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. 54 ATA8742 9151A-INDCO-07/09 ATA8742 16. System Control and Reset 16.0.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP - Relative Jump - instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 16-1 on page 56 shows the reset logic. Table 16-1 on page 57 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in "Clock Sources" on page 42. 16.0.2 Reset Sources The ATtiny24/44/84 has four sources of reset: * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). * External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled. * Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. * Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled. 55 9151A-INDCO-07/09 Figure 16-1. Reset Logic DATA BUS MCU Status Register (MCUSR) PORF BORF EXTRF WDRF Power-on Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER Brown-out Reset Circuit Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[1:0] SUT[1:0] 16.0.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in "System and Reset Characterizations" on page 198. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. Figure 16-2. MCU Start-up, RESET Tied to VCC V CCRR VCC VPORMA X VPORMIN RESET VRST TIME-OUT tTOUT INTERNAL RESET 56 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 16-3. MCU Start-up, RESET Extended Externally VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET Table 16-1. Symbol VPOT VPORMAX VPORMIN VCCRR VRST Note: Power On Reset Specifications Parameter Power-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling) VCC Max. start voltage to ensure internal Power-on Reset signal VCC Min. start voltage to ensure internal Power-on Reset signal VCC Rise Rate to ensure Power-on Reset RESET Pin Threshold Voltage -0.1 0.01 0.1 VCC 0.9VCC () Min 1.1 0.8 Typ 1.4 1.3 Max 1.7 1.6 0.4 Units V V V V V/ms V 1. Before rising, the supply has to be between VPORMIN and VPORMAX to ensure a Reset. 16.0.4 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see "System and Reset Characterizations" on page 198) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - VRST - on its positive edge, the delay counter starts the MCU after the Time-out period - tTOUT - has expired. 57 9151A-INDCO-07/09 Figure 16-4. External Reset During Operation CC 58 ATA8742 9151A-INDCO-07/09 ATA8742 16.0.5 Brown-out Detection ATtiny24/44/84 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure 16-5 on page 59), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (V BOT+ in Figure 16-5 on page 59), the delay counter starts the MCU after the Time-out period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in "System and Reset Characterizations" on page 198. Figure 16-5. Brown-out Reset During Operation VCC VBOTVBOT+ RESET TIME-OUT tTOUT INTERNAL RESET 16.0.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. See "Watchdog Timer" on page 60 for details on operation of the Watchdog Timer. Figure 16-6. Watchdog Reset During Operation CC CK 59 9151A-INDCO-07/09 16.1 Internal Voltage Reference ATtiny24/44/84 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 16.1.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in "System and Reset Characterizations" on page 198. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 16.2 Watchdog Timer The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 16-4 on page 64. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny24/44/84 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 16-4 on page 64. The watchdog timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 16-2. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 61 for details. Table 16-2. WDTON Unprogrammed Programmed WDT Configuration as a Function of the Fuse Settings of WDTON Safety Level 1 2 WDT Initial State Disabled Enabled How to Disable the WDT Timed sequence Always enabled How to Change Time-out No limitations Timed sequence 60 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 16-7. Watchdog Timer 128 kHz OSCILLATOR OSC/2K OSC/4K OSC/8K WATCHDOG PRESCALER OSC/1024K OSC/128K OSC/256K OSC/512K OSC/16K OSC/32K OSC/64K WATCHDOG RESET WDP0 WDP1 WDP2 WDP3 WDE MCU RESET 16.3 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 16.3.1 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared. 16.3.2 Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 61 9151A-INDCO-07/09 16.4 16.4.1 Register Description MCUSR - MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 0x34 (0x54) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR See Bit Description * Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 16.4.2 WDTCSR - Watchdog Timer Control and Status Register Bit 0x21 (0x41) Read/Write Initial Value 7 WDIF R/W 0 6 WDIE R/W 0 5 WDP3 R/W 0 4 WDCE R/W 0 3 WDE R/W X 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCSR * Bit 7 - WDIF: Watchdog Timeout Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. * Bit 6 - WDIE: Watchdog Timeout Interrupt Enable When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs. If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, 62 ATA8742 9151A-INDCO-07/09 ATA8742 the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 16-3. WDE 0 0 1 1 Watchdog Timer Configuration WDIE 0 1 0 1 Watchdog Timer State Stopped Running Running Running Action on Time-out None Interrupt Reset Interrupt * Bit 4 - WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. See the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 61. * Bit 3 - WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 61. In safety level 1, WDE is overridden by WDRF in MCUSR. See "MCUSR - MCU Status Register" on page 62 for description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Note: If the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. To avoid this situation, the application software should always clear the WDRF flag and the WDE control bit in the initialization routine. * Bits 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 16-4 on page 64. 63 9151A-INDCO-07/09 Table 16-4. WDP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Watchdog Timer Prescale Select WDP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 0 1 0 1 0 Reserved 1 1 1 1 0 1 Number of WDT Oscillator Cycles 2K cycles 4K cycles 8K cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1024K cycles Typical Time-out at VCC = 5.0V 16 ms 32 ms 64 ms 0.125 s 0.25 s 0.5 s 1.0 s 2.0 s 4.0 s 8.0 s WDP2 0 0 0 0 1 1 1 1 0 0 0 0 1 64 ATA8742 9151A-INDCO-07/09 ATA8742 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example(1) WDT_off: WDR ; Clear WDRF in MCUSR ldi out r16, (0< void WDT_off(void) { _WDR(); /* Clear WDRF in MCUSR */ MCUSR = 0x00 /* Write logical one to WDCE and WDE */ WDTCR |= (1< 9151A-INDCO-07/09 17. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny24/44/84. For a general explanation of the AVR interrupt handling, see "Reset and Interrupt Handling" on page 28. 17.1 Interrupt Vectors Table 17-1. Vector No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Reset and Interrupt Vectors Program Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 Source RESET INT0 PCINT0 PCINT1 WDT TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMPA TIMER0 COMPB TIMER0 OVF ANA_COMP ADC EE_RDY USI_START USI_OVF Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset External Interrupt Request 0 Pin Change Interrupt Request 0 Pin Change Interrupt Request 1 Watchdog Time-out Timer/Counter1 Capture Event Timer/Counter1 Compare Match A Timer/Counter1 Compare Match B Timer/Counter0 Overflow Timer/Counter0 Compare Match A Timer/Counter0 Compare Match B Timer/Counter0 Overflow Analog Comparator ADC Conversion Complete EEPROM Ready USI START USI Overflow If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny24/44/84 is: 66 ATA8742 9151A-INDCO-07/09 ATA8742 Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 ; 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 ... ... RESET: ldi out ldi out sei 67 9151A-INDCO-07/09 18. External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT11..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT11..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change 0 interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts PCI1 will trigger if any enabled PCINT11..8 pin toggles. The PCMSK0 and PCMSK1 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT11..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register - MCUCR. When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in "Clock Systems and their Distribution" on page 41. Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in "System Clock and Clock Options" on page 41. 18.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure . Timing of pin change interrupts PCINT(0) LE pin_lat D Q pcint_in_(0) pin_sync PCINT(0) in PCMSK(x) 0 x clk pcint_syn pcint_setflag PCIF clk clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 68 ATA8742 9151A-INDCO-07/09 ATA8742 18.2 18.2.1 Register Description MCUCR - MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 0x35 (0x55) Read/Write Initial Value 7 - R 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 - R 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 18-1 on page 69. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 18-1. ISC01 0 0 1 1 Interrupt 0 Sense Control ISC00 0 1 0 1 Description The low level of INT0 generates an interrupt request. Any logical change on INT0 generates an interrupt request. The falling edge of INT0 generates an interrupt request. The rising edge of INT0 generates an interrupt request. 18.2.2 GIMSK - General Interrupt Mask Register Bit 0x3B (0x5B) Read/Write Initial Value 7 - R 0 6 INT0 R/W 0 5 PCIE1 R/W 0 4 PCIE0 R/w 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIMSK * Bits 7, 3..0 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. * Bit 5 - PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT11..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT11..8 pins are enabled individually by the PCMSK1 Register. 69 9151A-INDCO-07/09 * Bit 4- PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register. 18.2.3 GIFR - General Interrupt Flag Register Bit 0x3A (0x5A Read/Write Initial Value 7 - R 0 6 INTF0 R/W 0 5 PCIF1 R/W 0 4 PCIF0 R/W 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIFR * Bits 7, 3..0 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bit 6 - INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. * Bit 5 - PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT11..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. * Bit 4- PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 18.2.4 PCMSK1 - Pin Change Mask Register 1 Bit 0x20 (0x40) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 PCINT11 R/W 0 2 PCINT10 R/W 0 1 PCINT9 R/W 0 0 PCINT8 R/W 0 PCMSK1 * Bits 7, 4- Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bits 3..0 - PCINT11..8: Pin Change Enable Mask 11..8 Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on 70 ATA8742 9151A-INDCO-07/09 ATA8742 the corresponding I/O pin. If PCINT11..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 18.2.5 PCMSK0 - Pin Change Mask Register 0 Bit 0x12 (0x32) Read/Write Initial Value 7 PCINT7 R/W 0 6 PCINT6 R/W 0 5 PCINT5 R/W 0 4 PCINT4 R/W 0 3 PCINT3 R/W 0 2 PCINT2 R/W 0 1 PCINT1 R/W 0 0 PCINT0 R/W 0 PCMSK0 * Bits 7..0 - PCINT7..0: Pin Change Enable Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 71 9151A-INDCO-07/09 19. I/O Ports 19.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 19-1 on page 72. See "Electrical Characteristics" on page 195 for a complete list of parameters. Figure 19-1. I/O Pin Equivalent Schematic Rpu Pxn Logic Cpin See Figure "General Digital I/O" for Details All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in "EXT_CLOCK = external clock is selected as system clock." on page 86. Three I/O memory address locations are allocated for each port, one each for the Data Register - PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable - PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in "Ports as General Digital I/O" on page 73. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in "Alternate Port Functions" on page 77. Refer to the individual module sections for a full description of the alternate functions. 72 ATA8742 9151A-INDCO-07/09 ATA8742 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 19.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 19-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 19-2. General Digital I/O(1) PUD Q D DDxn Q CLR RESET WDx RDx 1 Pxn Q D PORTxn Q CLR 0 RESET WRx SLEEP RRx WPx SYNCHRONIZER D Q D Q RPx PINxn L Q Q clk I/O PUD: SLEEP: clkI/O: PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WRx: RRx: RPx: WPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. 19.2.1 Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in "EXT_CLOCK = external clock is selected as system clock." on page 86, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. DATA BUS 73 9151A-INDCO-07/09 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 19.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 19.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 19-1 on page 74 summarizes the control signals for the pin value. Table 19-1. DDxn 0 0 0 1 1 Port Pin Configurations PUD (in MCUCR) X 0 1 X X I/O Input Input Input Output Output Pull-up No Yes No No No Comment Tri-state (Hi-Z) Pxn will source current if ext. pulled low. Tri-state (Hi-Z) Output Low (Sink) Output High (Source) PORTxn 0 1 1 0 1 19.2.4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 19-2 on page 73, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 19-3 on page 75 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. 74 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 19-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17 0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd, max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 11/2 system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 19-4 on page 75. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 19-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 0x00 t pd 0xFF out PORTx, r16 nop 0xFF in r17, PINx The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values 75 9151A-INDCO-07/09 are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out nop ; Read port pins in ... r16,PINA r16,(1< C Code Example unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTA = (1< Digital Input Enable and Sleep Modes As shown in Figure 19-2 on page 73, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in "Alternate Port Functions" on page 77. If a logic high level ("one") is present on an asynchronous external interrupt pin configured as "Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin" while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 76 ATA8742 9151A-INDCO-07/09 ATA8742 19.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 19.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 19-5 on page 78 shows how the port pin control signals from the simplified Figure 19-2 on page 73 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. 77 9151A-INDCO-07/09 Figure 19-5. Alternate Port Functions(1) PUOExn PUOVxn 1 0 PUD DDOExn DDOVxn 1 0 Q D DDxn Q CLR PVOExn PVOVxn WDx RESET RDx 1 Pxn 0 Q D 1 0 PORTxn PTOExn WPx DIEOExn DIEOVxn 1 0 Q CLR RESET RRx WRx SLEEP SYNCHRONIZER D SET RPx Q D Q PINxn L CLR Q CLR Q clk I/O DIxn AIOxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn: Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE PUD: WDx: RDx: RRx: WRx: RPx: WPx: clkI/O: DIxn: AIOxn: PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Table 19-2 on page 79 summarizes the function of the overriding signals. The pin and port indexes from Figure 19-5 on page 78 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. 78 ATA8742 9151A-INDCO-07/09 DATA BUS ATA8742 Table 19-2. Signal Name PUOE Generic Description of Overriding Signals for Alternate Functions Full Name Pull-up Override Enable Pull-up Override Value Data Direction Override Enable Data Direction Override Value Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits. If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit. If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit. If PTOE is set, the PORTxn Register bit is inverted. If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode). If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode). This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt-trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/Output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. PUOV DDOE DDOV PVOE Port Value Override Enable Port Value Override Value Port Toggle Override Enable Digital Input Enable Override Enable Digital Input Enable Override Value PVOV PTOE DIEOE DIEOV DI Digital Input AIO Analog Input/Output The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 79 9151A-INDCO-07/09 19.3.1 Alternate Functions of Port A The Port A pins with alternate function are shown in Table 19-7 on page 84. Table 19-3. Port A Pins Alternate Functions Alternate Function ADC0: ADC input channel 0. AREF: External analog reference. PCINT0: Pin change interrupt 0 source 0. ADC1: ADC input channel 1. AIN0: Analog Comparator Positive Input. PCINT1:Pin change interrupt 0 source 1. ADC2: ADC input channel 2. AIN1: Analog Comparator Negative Input. PCINT2: Pin change interrupt 0 source 2. ADC3: ADC input channel 3. T0: Timer/Counter0 counter source. PCINT3: Pin change interrupt 0 source 3. ADC4: PA4 ADC input channel 4. USCK: USI Clock three wire mode. SCL : USI Clock two wire mode. T1: Timer/Counter1 counter source. PCINT4: Pin change interrupt 0 source 4. ADC5: ADC input channel 5. DO: USI Data Output three wire mode. OC1B: Timer/Counter1 Compare Match B output. PCINT5: Pin change interrupt 0 source 5. ADC6: ADC input channel 6. DI: USI Data Input three wire mode. SDA: USI Data Input two wire mode. OC1A: Timer/Counter1 Compare Match A output. PCINT6: Pin change interrupt 0 source 6. ADC7: ADC input channel 7. OC0B: Timer/Counter0 Compare Match B output. ICP1: Timer/Counter1 Input Capture Pin. PCINT7: Pin change interrupt 0 source 7. Port Pin PA0 PA1 PA2 PA3 PA5 PA6 PA7 * Port A, Bit 0 - ADC0/AREF/PCINT0 ADC0: Analog to Digital Converter, Channel 0. AREF: External Analog Reference for ADC. Pull-up and output driver are disabled on PA0 when the pin is used as an external reference or Internal Voltage Reference with external capacitor at the AREF pin by setting (one) the bit REFS0 in the ADC Multiplexer Selection Register (ADMUX). PCINT0: Pin Change Interrupt source 0. The PA0 pin can serve as an external interrupt source for pin change interrupt 0. 80 ATA8742 9151A-INDCO-07/09 ATA8742 * Port A, Bit 1 - ADC1/AIN0/PCINT1 ADC1: Analog to Digital Converter, Channel 1. AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT1: Pin Change Interrupt source 1. The PA1 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 2 - ADC2/AIN1/PCINT2 ADC2: Analog to Digital Converter, Channel 2. AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT2: Pin Change Interrupt source 2. The PA2 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 3 - ADC3/T0/PCINT3 ADC3: Analog to Digital Converter, Channel 3. T0: Timer/Counter0 counter source. PCINT3: Pin Change Interrupt source 3. The PA3 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 4 - ADC4/USCK/SCL/T1/PCINT4 ADC4: Analog to Digital Converter, Channel 4. USCK: Three-wire mode Universal Serial Interface Clock. SCL: Two-wire mode Serial Clock for USI Two-wire mode. T1: Timer/Counter1 counter source. PCINT4: Pin Change Interrupt source 4. The PA4 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 5 - ADC5/DO/OC1B/PCINT5 ADC5: Analog to Digital Converter, Channel 5. DO: Data Output in USI Three-wire mode. Data output (DO) overrides PORTA5 value and it is driven to the port when the data direction bit DDA5 is set (one). However the PORTA5 bit still controls the pullup, enabling pullup if direction is input and PORTA5 is set(one). OC1B: Output Compare Match output: The PA5 pin can serve as an external output for the Timer/Counter1 Compare Match B. The PA5 pin has to be configured as an output (DDA5 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT5: Pin Change Interrupt source 5. The PA5 pin can serve as an external interrupt source for pin change interrupt 0. 81 9151A-INDCO-07/09 * Port A, Bit 6 - ADC6/DI/SDA/OC1A/PCINT6 ADC6: Analog to Digital Converter, Channel 6. SDA: Two-wire mode Serial Interface Data. DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. OC1A, Output Compare Match output: The PA6 pin can serve as an external output for the Timer/Counter1 Compare Match A. The PA6 pin has to be configured as an output (DDA6 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT6: Pin Change Interrupt source 6. The PA6 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 7 - ADC7/OC0B/ICP1/PCINT7 ADC7: Analog to Digital Converter, Channel 7. OC1B, Output Compare Match output: The PA7 pin can serve as an external output for the Timer/Counter1 Compare Match B. The PA7 pin has to be configured as an output (DDA7 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. ICP1, Input Capture Pin: The PA7 pin can act as an Input Capture Pin for Timer/Counter1. PCINT7: Pin Change Interrupt source 7. The PA7 pin can serve as an external interrupt source for pin change interrupt 0. Table 19-4 on page 82 to Table 19-6 on page 83 relate the alternate functions of Port A to the overriding signals shown in Figure 19-5 on page 78. Table 19-4. Signal Name PUOE PUOV DDOE DDOV PVOE Overriding Signals for Alternate Functions in PA7..PA5 PA6/ADC6/DI/SDA/OC1A/ PCINT6 0 0 USIWM1 (SDA + PORTA6) * DDRA6 (USIWM1 * DDA6) + OC1A enable ( USIWM1* DDA6) * OC1A 0 USISIE + (PCINT6 * PCIE0) + ADC6D USISIE + PCINT7 * PCIE0 DI/SDA/PCINT6 Input ADC6 Input PA5/ADC5/DO/OC1B/ PCINT5 0 0 0 0 (USIWM1 * USIWM0) + OC1B enable USIWM1 * USIWM0 * DO + (~USIWM1 * USIWM0) * OC1B} 0 PCINT5 * PCIE + ADC5D PCINT5 * PCIE PCINT5 Input ADC5 Input PA7/ADC7/OC0B/ICP1/ PCINT7 0 0 0 0 OC0B enable PVOV PTOE DIEOE DIEOV DI AIO OC0B 0 PCINT7 * PCIE0 + ADC7D PCINT7 * PCIE0 PCINT7/ICP1 Input ADC7 Input 82 ATA8742 9151A-INDCO-07/09 ATA8742 Table 19-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Overriding Signals for Alternate Functions in PA4..PA2 PA3/ADC3/T0/PCINT3 0 0 0 0 0 0 0 (PCINT3 * PCIE0) + ADC3D PCINT3 * PCIE0 PCINT1 Input ADC3 Input PA2/ADC2/AIN1/PCINT2 0 0 0 0 0 0 0 PCINT2 * PCIE + ADC2D PCINT3 * PCIE0 PCINT0 Input ADC2/Analog Comparator Negative Input PA4/ADC4/USCK/SCL/T1/P CINT4 0 0 USIWM1 USI_SCL_HOLD + PORTA4) * ADC4D USIWM1 * ADC4D 0 USI_PTOE USISIE + (PCINT4 * PCIE0) + ADC4D USISIE + (PCINT4 * PCIE0) USCK/SCL/T1/PCINT4 input ADC4 Input Table 19-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Overriding Signals for Alternate Functions in PA1..PA0 PA1/ADC1/AIN0/PCINT1 PA0/ADC0/AREF/PCINT0 0 0 0 0 0 0 0 PCINT1 * PCIE0 + ADC1D PCINT1 * PCIE0 PCINT1 Input ADC1/Analog Comparator Positive Input RESET * (REFS1 * REFS0 + REFS1 * REFS0) 0 RESET * (REFS1 * REFS0 + REFS1 * REFS0) 0 RESET * (REFS1 * REFS0 + REFS1 * REFS0) 0 0 PCINT0 * PCIE0 + ADC0D PCINT0 * PCIE0 PCINT0 Input ADC1 Input Analog reference 83 9151A-INDCO-07/09 19.3.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 19-7 on page 84. Table 19-7. Port B Pins Alternate Functions Alternate Function XTAL1: Crystal Oscillator Input. PCINT8: Pin change interrupt 1 source 8. XTAL2: Crystal Oscillator Output. PCINT9: Pin change interrupt 1 source 9. INT0: External Interrupt 0 Input. OC0A: Timer/Counter0 Compare Match A output. CKOUT: System clock output. PCINT10:Pin change interrupt 1 source 10. RESET: Reset pin. dW: debugWire I/O. PCINT11:Pin change interrupt 1 source 11. Port Pin PB0 PB1 PB2 PB3 * Port B, Bit 0 - XTAL1/PCINT8 XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal calibratable RC oscillator. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator as a chip clock source, PB0 serves as an ordinary I/O pin. PCINT8: Pin Change Interrupt source 8. The PB0 pin can serve as an external interrupt source for pin change interrupt 1. * Port B, Bit 1 - XTAL2/PCINT9 XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibratable RC Oscillator and external clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator or External clock as a Chip clock sources, PB1 serves as an ordinary I/O pin. PCINT9: Pin Change Interrupt source 9. The PB1 pin can serve as an external interrupt source for pin change interrupt 1. * Port B, Bit 2 - INT0/OC0A/CKOUT/PCINT10 INT0: External Interrupt Request 0. OC0A: Output Compare Match output: The PB2 pin can serve as an external output for the Timer/Counter0 Compare Match A. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function. CKOUT - System Clock Output: The system clock can be output on the PB2 pin. The system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB2 and DDB2 settings. It will also be output during reset. PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interrupt source for pin change interrupt 1. 84 ATA8742 9151A-INDCO-07/09 ATA8742 * Port B, Bit 3 - RESET/dW/PCINT11 RESET: External Reset input is active low and enabled by unprogramming ("1") the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. PCINT11: Pin Change Interrupt source 11. The PB3 pin can serve as an external interrupt source for pin change interrupt 1. Table 19-8 on page 85 and Table 19-9 on page 86 relate the alternate functions of Port B to the overriding signals shown in Figure 19-5 on page 78. Table 19-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 1. 2. Overriding Signals for Alternate Functions in PB3..PB2 PB3/RESET/dW/ PCINT11 RSTDISBL (1)+ DEBUGWIRE_ENABLE (2) 1 RSTDISBL (1) PB2/INT0/OC0A/CKOUT/PCINT10 CKOUT 0 + DEBUGWIRE_ENABLE (2) CKOUT 1'b1 CKOUT + OC0A enable CKOUT * System Clock + CKOUT * OC0A 0 DEBUGWIRE_ENABLE(2) * debugWire Transmit RSTDISBL(1) + DEBUGWIRE_ENABLE(2) 0 0 RSTDISBL + DEBUGWIRE_ENABLE PCINT11 * PCIE1 (1) (2) + PCINT10 * PCIE1 + INT0 PCINT10 * PCIE1 + INT0 INT0/PCINT10 Input DEBUGWIRE_ENABLE(2) + (RSTDISBL(1) * PCINT11 * PCIE1) dW/PCINT11 Input RSTDISBL is 1 when the Fuse is "0" (Programmed). DebugWIRE is enabled when DWEN Fuse is programmed and Lock bits are unprogrammed. 85 9151A-INDCO-07/09 Table 19-9. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 1. 2. Overriding Signals for Alternate Functions in PB1..PB0 PB1/XTAL2/PCINT9 EXT_OSC 0 EXT_OSC(1) 0 EXT_OSC 0 0 EXT_OSC (1)+ PCINT9 * PCIE1 EXT_OSC(1) * PCINT9 * PCIE1 PCINT9 Input XTAL2 (1) (1) PB0/XTAL1/PCINT8 EXT_CLOCK (2) + EXT_OSC(1) 0 EXT_CLOCK(2) + EXT_OSC(1) 0 EXT_CLOCK(2) + EXT_OSC(1) 0 0 EXT_CLOCK(2) + EXT_OSC(1) + (PCINT8 * PCIE1) ( EXT_CLOCK(2) * PWR_DOWN ) + (EXT_CLOCK(2) * EXT_OSC(1) * PCINT8 * PCIE1) CLOCK/PCINT8 Input XTAL1 EXT_OSC = crystal oscillator or low frequency crystal oscillator is selected as system clock. EXT_CLOCK = external clock is selected as system clock. 86 ATA8742 9151A-INDCO-07/09 ATA8742 19.4 19.4.1 Register Description MCUCR - MCU Control Register Bit 7 - Read/Write Initial Value R 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 - R 0 1 ISC01 R 0 0 ISC00 R 0 MCUCR * Bits 7, 2- Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bit 6 - PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See "Configuring the Pin" on page 73 for more details about this feature. 19.4.2 PORTA - Port A Data Register Bit 0x1B (0x3B) Read/Write Initial Value 7 PORTA7 6 PORTA6 5 PORTA5 4 PORTA4 3 PORTA3 2 PORTA2 1 PORTA1 0 PORTA0 PORTA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 19.4.3 DDRA - Port A Data Direction Register Bit 0x1A (0x3A) Read/Write Initial Value 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRB 19.4.4 PINA - Port A Input Pins Address Bit 0x19 (0x39) Read/Write Initial Value 7 PINA7 R/W 0 6 PINA6 R/W 0 5 PINA5 R/W N/A 4 PINA4 R/W N/A 3 PINA3 R/W N/A 2 PINA2 R/W N/A 1 PINA1 R/W N/A 0 PINA0 R/W N/A PINB 19.4.5 PORTB - Port B Data Register Bit 0x18 (0x38) Read/Write Initial Value 7 - 6 - 5 4 3 PORTB3 2 PORTB2 1 PORTB1 0 PORTB0 PORTB R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 19.4.6 DDRB - Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial Value 7 - 6 - 5 4 3 DDB3 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB R 0 R 0 R 0 R 0 R/W 0 87 9151A-INDCO-07/09 19.4.7 PINB - Port BInput Pins Address Bit 0x16 (0x36) Read/Write Initial Value 7 - 6 - 5 4 3 PINB3 2 PINB2 R/W N/A 1 PINB1 R/W N/A 0 PINB0 R/W N/A PINB R 0 R 0 R N/A R N/A R/W N/A 88 ATA8742 9151A-INDCO-07/09 ATA8742 20. 8-bit Timer/Counter0 with PWM 20.1 Features * * * * * * * Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) 20.2 Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 20-1 on page 89. For the actual placement of I/O pins. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "Register Description" on page 100. Figure 20-1. 8-bit Timer/Counter Block Diagram Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) = OCRnA Fixed TOP Value Waveform Generation OCnA DATA BUS OCnB (Int.Req.) Waveform Generation OCnB = OCRnB TCCRnA TCCRnB 20.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter 89 9151A-INDCO-07/09 uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See "Output Compare Unit" on page 91 for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. 20.2.2 Definitions Many register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 0. A lower case "x" replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 20-1 on page 90 are also used extensively throughout the document. Table 20-1. BOTTOM MAX TOP Definitions The counter reaches the BOTTOM when it becomes 0x00. The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation. 20.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and prescaler, see "Timer/Counter Prescaler" on page 136. 20.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 20-2 on page 90 shows a block diagram of the counter and its surroundings. Figure 20-2. Counter Unit Block Diagram DATA BUS TOVn (Int.Req.) Clock Select count TCNTn clear direction ( From Prescaler ) bottom top Control Logic clkTn Edge Detector Tn 90 ATA8742 9151A-INDCO-07/09 ATA8742 Signal description (internal signals): count direction clear clkTn top bottom Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). Timer/Counter clock, referred to as clkT0 in the following. Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 94. The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt. 20.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation. See "Modes of Operation" on page 94. Figure 20-3 on page 92 shows a block diagram of the Output Compare unit. 91 9151A-INDCO-07/09 Figure 20-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom FOCn Waveform Generator OCnx WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly. 20.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled). 20.5.2 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 20.5.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform 92 ATA8742 9151A-INDCO-07/09 ATA8742 generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 20.6 Compare Match Output Unit The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 20-4 on page 93 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to "0". Figure 20-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCn Pin OCnx D DATA BUS 0 Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation, see "Register Description" on page 100 93 9151A-INDCO-07/09 20.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 20-2 on page 100. For fast PWM mode, refer to Table 20-3 on page 100, and for phase correct PWM refer to Table 20-4 on page 101. A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the 0x strobe bits. 20.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See "Modes of Operation" on page 94). For detailed timing information refer to Figure 20-8 on page 98, Figure 20-9 on page 99, Figure 20-10 on page 99 and Figure 20-11 on page 99 in "Timer/Counter Timing Diagrams" on page 98. 20.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 20.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 20-5 on page 95. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 94 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 20-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period 1 2 3 4 (COMnx1:0 = 1) An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of 0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = -----------------------------------------------------2 N ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 20.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 95 9151A-INDCO-07/09 PWM mode is shown in Figure 20-6 on page 96. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 20-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn OCn (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 20-3 on page 100). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = -------------------N 256 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of 0 = fclk_I/O/2 when OCR0A is set to zero. This fea- 96 ATA8742 9151A-INDCO-07/09 ATA8742 ture is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 20.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 20-7 on page 97. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 20-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn OCn (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to 97 9151A-INDCO-07/09 one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 20-4 on page 101). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = -------------------N 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 20-7 on page 97 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. * OCR0A changes its value from MAX, like in Figure 20-7 on page 97. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. * The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 20.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 20-8 on page 98 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 20-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 20-9 on page 99 shows the same timing data, but with the prescaler enabled. 98 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 20-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 20-10 on page 99 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 20-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 20-11 on page 99 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 20-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) OCRnx TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFnx 99 9151A-INDCO-07/09 20.9 20.9.1 Register Description TCCR0A - Timer/Counter Control Register A Bit 0x30 (0x50) Read/Write Initial Value 7 COM0A1 6 COM0A0 5 COM0B1 4 COM0B0 3 - 2 - 1 WGM01 0 WGM00 TCCR0A R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 * Bits 7:6 - COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. Table 20-2 on page 100 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 20-2. COM01 0 0 1 1 Compare Output Mode, non-PWM Mode COM00 0 1 0 1 Description Normal port operation, OC0A disconnected. Toggle OC0A on Compare Match Clear OC0A on Compare Match Set OC0A on Compare Match Table 20-3 on page 100 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 20-3. COM01 0 0 1 1 Note: Compare Output Mode, Fast PWM Mode(1) COM00 0 1 0 1 Description Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. Clear OC0A on Compare Match, set OC0A at BOTTOM (non-inverting mode) Set OC0A on Compare Match, clear OC0A at BOTTOM (inverting mode) 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Fast PWM Mode" on page 95 for more details. 100 ATA8742 9151A-INDCO-07/09 ATA8742 Table 20-4 on page 101 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 20-4. COM0A1 0 0 1 1 Note: Compare Output Mode, Phase Correct PWM Mode(1) COM0A0 0 1 0 1 Description Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 97 for more details. * Bits 5:4 - COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. Table 20-2 on page 100 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 20-5. COM01 0 0 1 1 Compare Output Mode, non-PWM Mode COM00 0 1 0 1 Description Normal port operation, OC0B disconnected. Toggle OC0B on Compare Match Clear OC0B on Compare Match Set OC0B on Compare Match Table 20-3 on page 100 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode. Table 20-6. COM01 0 0 1 1 Compare Output Mode, Fast PWM Mode(1) COM00 0 1 0 1 Description Normal port operation, OC0B disconnected. Reserved Clear OC0B on Compare Match, set OC0B at BOTTOM (non-inverting mode) Set OC0B on Compare Match, clear OC0B at BOTTOM (inverting mode) 101 9151A-INDCO-07/09 Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See "Fast PWM Mode" on page 95 for more details. Table 20-4 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 20-7. COM0A1 0 0 1 1 Note: Compare Output Mode, Phase Correct PWM Mode(1) COM0A0 0 1 0 1 Description Normal port operation, OC0B disconnected. Reserved Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 97 for more details. * Bits 3, 2 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bits 1:0 - WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 20-8 on page 102. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see "Modes of Operation" on page 94). Table 20-8. Waveform Generation Mode Bit Description Timer/Counter Mode of Operation Normal PWM, Phase Correct CTC Fast PWM Reserved PWM, Phase Correct Reserved Fast PWM Update of OCRx at Immediate TOP Immediate BOTTOM - TOP - BOTTOM TOV Flag Set on(1) MAX BOTTOM MAX MAX - BOTTOM - TOP Mode 0 1 2 3 4 5 6 7 Note: WGM2 0 0 0 0 1 1 1 1 WGM1 0 0 1 1 0 0 1 1 WGM0 0 1 0 1 0 1 0 1 TOP 0xFF 0xFF OCRA 0xFF - OCRA - OCRA 1. MAX = 0xFF BOTTOM = 0x00 102 ATA8742 9151A-INDCO-07/09 ATA8742 20.9.2 TCCR0B - Timer/Counter Control Register B Bit 0x33 (0x53) Read/Write Initial Value 7 FOC0A 6 FOC0B 5 - 4 - 3 WGM02 2 CS02 1 CS01 0 CS00 TCCR0B W 0 W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 * Bit 7 - FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. * Bit 6 - FOC0B: Force Output Compare B The FOC0B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare. A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. * Bits 5:4 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bit 3 - WGM02: Waveform Generation Mode See the description in the "TCCR0A - Timer/Counter Control Register A" on page 100. * Bits 2:0 - CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. 103 9151A-INDCO-07/09 Table 20-9. CS02 0 0 0 0 1 1 1 1 Clock Select Bit Description CS00 0 1 0 1 0 1 0 1 Description No clock source (Timer/Counter stopped) clkI/O/(No prescaling) clkI/O/8 (From prescaler) clkI/O/64 (From prescaler) clkI/O/256 (From prescaler) clkI/O/1024 (From prescaler) External clock source on T0 pin. Clock on falling edge. External clock source on T0 pin. Clock on rising edge. CS01 0 0 1 1 0 0 1 1 If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 20.9.3 TCNT0 - Timer/Counter Register Bit 0x32 (0x52) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 TCNT0 R/W 0 R/W 0 R/W 0 TCNT0[7:0] R/W 0 R/W 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers. 20.9.4 OCR0A - Output Compare Register A Bit 0x36 (0x56) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 OCR0A R/W 0 R/W 0 R/W 0 OCR0A[7:0] R/W 0 R/W 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 20.9.5 OCR0B - Output Compare Register B Bit 0x3C (0x5C) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 OCR0B R/W 0 R/W 0 R/W 0 OCR0B[7:0] R/W 0 R/W 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 104 ATA8742 9151A-INDCO-07/09 ATA8742 20.9.6 TIMSK0 - Timer/Counter 0 Interrupt Mask Register Bit 0x39 (0x59) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 OCIE0B R/W 0 1 OCIE0A R/W 0 0 TOIE0 R/W 0 TIMSK0 * Bits 7..3 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bit 2- OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register - TIFR0. * Bit 1- OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register - TIFR0. * Bit 0- TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register - TIFR0. 20.9.7 TIFR0 - Timer/Counter 0 Interrupt Flag Register Bit 0x38 (0x58) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 OCF0B R/W 0 1 OCF0A R/W 0 0 TOV0 R/W 0 TIFR0 * Bits 7..3 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. * Bit 2- OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B - Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed. * Bit 1- OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A - Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. 105 9151A-INDCO-07/09 * Bit 0- TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. See Table 20-8 on page 102 and "Waveform Generation Mode Bit Description" on page 102. 106 ATA8742 9151A-INDCO-07/09 ATA8742 21. 16-bit Timer/Counter1 21.1 Features * * * * * * * * * * * True 16-bit Design (i.e., Allows 16-bit PWM) Two independent Output Compare Units Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceler Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator External Event Counter Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1) 21.2 Overview The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. Most register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, and a lower case "x" replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 21-1 on page 108. For the actual placement of I/O pins. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "Register Description" on page 129. 107 9151A-INDCO-07/09 Figure 21-1. 16-bit Timer/Counter Block Diagram Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) = OCRnA Fixed TOP Values Waveform Generation OCnA DATA BUS OCnB (Int.Req.) Waveform Generation OCnB = OCRnB ICFn (Int.Req.) Edge Detector ( From Analog Comparator Ouput ) ICRn Noise Canceler ICPn TCCRnA TCCRnB 21.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section "Accessing 16-bit Registers" on page 110. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1). The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See "Output Compare Units" on page 116. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. 108 ATA8742 9151A-INDCO-07/09 ATA8742 The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See "Analog Comparator" on page 150). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output. 21.2.2 Definitions The following definitions are used extensively throughout the section: BOTTOM MAX The counter reaches the BOTTOM when it becomes 0x0000. The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation. TOP 21.2.3 Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: * All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. * Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. * Interrupt Vectors. The following control bits have changed name, but have same functionality and register location: * PWM10 is changed to WGM10. * PWM11 is changed to WGM11. * CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: * 1A and 1B are added to TCCR1A. * WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. 109 9151A-INDCO-07/09 21.3 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using "C", the compiler handles the 16-bit access. Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: 1. See "About Code Examples" on page 22. The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the 110 ATA8742 9151A-INDCO-07/09 ATA8742 main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. See "About Code Examples" on page 22. The assembly code example returns the TCNT1 value in the r17:r16 register pair. 111 9151A-INDCO-07/09 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example(1) TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1. See "About Code Examples" on page 22. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 21.3.1 Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. 21.4 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see "Timer/Counter Prescaler" on page 136. 112 ATA8742 9151A-INDCO-07/09 ATA8742 21.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 21-2 on page 113 shows a block diagram of the counter and its surroundings. Figure 21-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction Control Logic clkTn Edge Detector Tn TCNTn (16-bit Counter) ( From Prescaler ) TOP BOTTOM Signal description (internal signals): Count Direction Clear clkT1 TOP BOTTOM Increment or decrement TCNT1 by 1. Select between increment and decrement. Clear TCNT1 (set all bits to zero). Timer/Counter clock. Signalize that TCNT1 has reached maximum value. Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 119. 113 9151A-INDCO-07/09 The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 21.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 21-3 on page 114. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small "n" in register and bit names indicates the Timer/Counter number. Figure 21-3. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) ICRn (16-bit Register) TCNTn (16-bit Counter) ACO* Analog Comparator ICPn ACIC* ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter's TOP value. In these cases the Waveform Genera- 114 ATA8742 9151A-INDCO-07/09 ATA8742 tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 110. 21.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 22-1 on page 136). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. 21.6.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 21.6.3 Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be 115 9151A-INDCO-07/09 cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used). 21.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation ("Modes of Operation" on page 119). A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 21-4 on page 116 shows a block diagram of the Output Compare unit. The small "n" in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the "x" indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 21-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) OCRnx Buffer (16-bit Register) TCNTn (16-bit Counter) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator OCnx WGMn3:0 COMnx1:0 The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization 116 ATA8742 9151A-INDCO-07/09 ATA8742 prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 110. 21.7.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (1x) bit. Forcing compare match will not set the OCF1x flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or toggled). 21.7.2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. 21.7.3 Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting. The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare (1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 117 9151A-INDCO-07/09 21.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 21-5 on page 118 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset occur, the OC1x Register is reset to "0". Figure 21-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx Pin OCnx D DATA BUS 0 Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. See Table 21-1 on page 129, Table 21-2 on page 129 and Table 21-3 on page 130 for details. The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See "Register Description" on page 129 The COM1x1:0 bits have no effect on the Input Capture unit. 118 ATA8742 9151A-INDCO-07/09 ATA8742 21.8.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 21-1 on page 129. For fast PWM mode refer to Table 21-2 on page 129, and for phase correct and phase and frequency correct PWM refer to Table 21-3 on page 130. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the 1x strobe bits. 21.9 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare match ("Compare Match Output Unit" on page 118) For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 126. 21.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 21.9.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. 119 9151A-INDCO-07/09 The timing diagram for the CTC mode is shown in Figure 21-6 on page 120. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 21-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period 1 2 3 4 (COMnA1:0 = 1) An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum frequency of 1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation: f clk_I/O f OCnA = ------------------------------------------------------2 N ( 1 + OCRnA ) The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 21.9.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor- 120 ATA8742 9151A-INDCO-07/09 ATA8742 rect and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R FPWM = ---------------------------------log ( 2 ) In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 21-7 on page 121. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 21-7. Fast PWM Mode, Timing Diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low 121 9151A-INDCO-07/09 value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 21-2 on page 129). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ------------------------------------N ( 1 + TOP ) The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). The waveform generated will have a maximum frequency of 1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 21.9.4 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. 122 ATA8742 9151A-INDCO-07/09 ATA8742 The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R PCPWM = ---------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 21-8 on page 123. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 21-8. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 21-8 on page 123 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can 123 9151A-INDCO-07/09 result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 21-3 on page 130). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 21.9.5 Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 21-8 on page 123 and Figure 21-9 on page 125). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and 124 ATA8742 9151A-INDCO-07/09 ATA8742 the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ---------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 21-9 on page 125. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 21-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 21-9 on page 125 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. 125 9151A-INDCO-07/09 Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 21-3 on page 130). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: f clk_I/O f OCnxPFCPWM = --------------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 21.10 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 21-10 on page 126 shows a timing diagram for the setting of OCF1x. Figure 21-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 21-11 on page 127 shows the same timing data, but with the prescaler enabled. 126 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 21-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 21-12 on page 127 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. Figure 21-12. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 21-13 on page 128 shows the same timing data, but with the prescaler enabled. 127 9151A-INDCO-07/09 Figure 21-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clk I/O clk Tn (clk /8) I/O TCNTn (CTC and FPWM) TOP - 1 TOP - 1 TOP BOTTOM BOTTOM + 1 TCNTn (PC and PFC PWM) TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value 128 ATA8742 9151A-INDCO-07/09 ATA8742 21.11 Register Description 21.11.1 TCCR1A - Timer/Counter1 Control Register A Bit 0x2F (0x4F) Read/Write Initial Value 7 COM1A1 6 COM1A0 5 COM1B1 4 COM1B0 3 - 2 - 1 WGM11 0 WGM10 TCCR1A R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 * Bit 7:6 - COM1A1:0: Compare Output Mode for Channel A * Bit 5:4 - COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 21-1 on page 129 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 21-1. Compare Output Mode, non-PWM COM1A0/COM1B0 0 1 0 1 Description Normal port operation, OC1A/OC1B disconnected. Toggle OC1A/OC1B on Compare Match. Clear OC1A/OC1B on Compare Match (Set output to low level). Set OC1A/OC1B on Compare Match (Set output to high level). COM1A1/COM1B1 0 0 1 1 Table 21-2 on page 129 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 21-2. Compare Output Mode, Fast PWM(1) COM1A0/COM1B0 0 Description Normal port operation, OC1A/OC1B disconnected. WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM (non-inverting mode) Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM (inverting mode) COM1A1/COM1B1 0 0 1 1 1 Note: 0 1 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. "Fast PWM Mode" on page 120 for more details. 129 9151A-INDCO-07/09 Table 21-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 21-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(Note:) COM1A0/COM1B0 0 Description Normal port operation, OC1A/OC1B disconnected. WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. Clear OC1A/OC1B on Compare Match when up-counting. Set OC1A/OC1B on Compare Match when downcounting. Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B on Compare Match when downcounting. COM1A1/COM1B1 0 0 1 1 0 1 1 Note: A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. "Phase Correct PWM Mode" on page 122 for more details. * Bit 1:0 - WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 21-4 on page 131. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. ("Modes of Operation" on page 119). 130 ATA8742 9151A-INDCO-07/09 ATA8742 Table 21-4. Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: Waveform Generation Mode Bit Description(1) WGM12 (CTC1) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGM11 (PWM11) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGM10 (PWM10) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Timer/Counter Mode of Operation Normal PWM, Phase Correct, 8-bit PWM, Phase Correct, 9-bit PWM, Phase Correct, 10-bit CTC Fast PWM, 8-bit Fast PWM, 9-bit Fast PWM, 10-bit PWM, Phase and Frequency Correct PWM, Phase and Frequency Correct PWM, Phase Correct PWM, Phase Correct CTC (Reserved) Fast PWM Fast PWM TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCR1A 0x00FF 0x01FF 0x03FF ICR1 OCR1A ICR1 OCR1A ICR1 - ICR1 OCR1A Update of OCR1x at Immediate TOP TOP TOP Immediate BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM TOP TOP Immediate - BOTTOM BOTTOM TOV1 Flag Set on MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP WGM13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. 21.11.2 TCCR1B - Timer/Counter1 Control Register B Bit 0x2E (0x4E) Read/Write Initial Value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 - R 0 4 WGM13 R/W 0 3 WGM12 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B * Bit 7 - ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. * Bit 6 - ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. 131 9151A-INDCO-07/09 When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. * Bit 5 - Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. * Bit 4:3 - WGM13:2: Waveform Generation Mode See TCCR1A Register description. * Bit 2:0 - CS12:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 21-10 and Figure 21-11. Table 21-5. CS12 0 0 0 0 1 1 1 1 Clock Select Bit Description CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 Description No clock source (Timer/Counter stopped). clkI/O/1 (No prescaling) clkI/O/8 (From prescaler) clkI/O/64 (From prescaler) clkI/O/256 (From prescaler) clkI/O/1024 (From prescaler) External clock source on T1 pin. Clock on falling edge. External clock source on T1 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 21.11.3 TCCR1C - Timer/Counter1 Control Register C Bit 0x22 (0x42) Read/Write Initial Value 7 FOC1A W 0 6 FOC1B W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 TCCR1C * Bit 7 - FOC1A: Force Output Compare for Channel A * Bit 6 - FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. 132 ATA8742 9151A-INDCO-07/09 ATA8742 A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. * Bit 5..0 - Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when the register is written. 21.11.4 TCNT1H and TCNT1L - Timer/Counter1 Bit 0x2D (0x4D) 0x2C (0x4C) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 TCNT1H TCNT1L R/W 0 R/W 0 R/W 0 TCNT1[15:8] TCNT1[7:0] R/W 0 R/W 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 110. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. 21.11.5 OCR1AH and OCR1AL - Output Compare Register 1 A Bit 0x2B (0x4B) 0x2A (0x4A) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 OCR1AH OCR1AL R/W 0 R/W 0 R/W 0 OCR1A[15:8] OCR1A[7:0] R/W 0 R/W 0 21.11.6 OCR1BH and OCR1BL - Output Compare Register 1 B Bit 0x29 (0x49) 0x28 (0x48) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 OCR1BH OCR1BL R/W 0 R/W 0 R/W 0 OCR1B[15:8] OCR1B[7:0] R/W 0 R/W 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 110. 133 9151A-INDCO-07/09 21.11.7 ICR1H and ICR1L - Input Capture Register 1 Bit 0x25 (0x45) 0x24 (0x44) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 ICR1[15:8] ICR1[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 ICR1H ICR1L The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. "Accessing 16-bit Registers" on page 110. 21.11.8 TIMSK1 - Timer/Counter Interrupt Mask Register 1 Bit 0x0C (0x2C) Read/Write Initial Value 7 - R 0 6 - R 0 5 ICIE1 R/W 0 4 - R 0 3 - R 0 2 OCIE1B R/W 0 1 OCIE1A R/W 0 0 TOIE1 R/W 0 TIMSK1 * Bit 7,6,4,3 - Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when the register is written. * Bit 5 - ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 66.) is executed when the ICF1 Flag, located in TIFR1, is set. * Bit 2- OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 66) is executed when the OCF1B flag, located in TIFR1, is set. * Bit 1- OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 66) is executed when the OCF1A flag, located in TIFR1, is set. * Bit 0 - TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (see "Interrupts" on page 66) is executed when the TOV1 flag, located in TIFR1, is set. 134 ATA8742 9151A-INDCO-07/09 ATA8742 21.11.9 TIFR1 - Timer/Counter Interrupt Flag Register 1 Bit 0x0B (0x2B) Read/Write Initial Value - R 0 7 - R 0 6 5 ICIF1 R/W 0 - R 0 4 - R 0 3 2 OCF1B R/W 0 1 OCF1A R/W 0 0 TOV1 R/W 0 TIFR1 * Bit 7,6,4,3 - Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when the register is written. * Bit 5- ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. * Bit 2- OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. * Bit 1- OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (1A) strobe will not set the OCF1A flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. * Bit 0- TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1 flag is set when the timer overflows. See Table 21-4 on page 131 for the TOV1 flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 135 9151A-INDCO-07/09 22. Timer/Counter Prescaler Timer/Counter 0, and 1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1. The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. 22.0.1 Prescaler Reset The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter's clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. 22.0.2 External Clock Source An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 22-1 on page 136 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 22-1. T0 Pin Sampling Tn D LE Q D Q D Q Tn_sync (To Clock Select Logic) clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys136 ATA8742 9151A-INDCO-07/09 ATA8742 tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 22-2. Prescaler for Timer/Counter0 clk I/O Clear PSR10 T0 Synchronization clkT0 Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 22-1 on page 136. 22.1 22.1.1 Register Description GTCCR - General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 PSR10 R/W 0 GTCCR * Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting. * Bit 0 - PSR10: Prescaler 0 Reset Timer/Counter n When this bit is one, the Timer/Countern prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. 137 9151A-INDCO-07/09 23. USI - Universal Serial Interface 23.1 Features * * * * * * Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wake-up from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability 23.2 Overview The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. A simplified block diagram of the USI is shown in Figure 23-1 on page 138. For the actual placement of I/O pins. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "Register Descriptions" on page 146. Figure 23-1. Universal Serial Interface, Block Diagram DQ LE DO (Output only) DI/SDA (Input/Open Drain) Bit7 Bit0 USIDR 3 2 1 0 TIM0 COMP USIOIF USISIF USIDC USIPF 4-bit Counter 3 2 1 0 [1] 0 1 CLOCK HOLD USCK/SCL (Input/Open Drain) DATA BUS USISR Two-wire Clock Control Unit 2 USIWM1 USIWM0 USICS1 USICS0 USICLK USIOIE USISIE USICR The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and outgoing data. The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The most significant bit is connected to one of two output pins depending of the wire mode configuration. A transparent latch is inserted between the Serial Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. 138 ATA8742 9151A-INDCO-07/09 USITC ATA8742 The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. 23.3 23.3.1 Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and USCK. Figure 23-2. Three-wire Mode Operation, Simplified Diagram DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DI USCK SLAVE DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DI USCK PORTxn MASTER Figure 23-2 on page 139 shows two USI units operating in Three-wire mode, one as Master and one as Slave. The two Shift Registers are interconnected in such way that after eight USCK clocks, the data in each register are interchanged. The same clock also increments the USI's 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. 139 9151A-INDCO-07/09 Figure 23-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK DO DI MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB ( Reference ) 1 2 3 4 5 6 7 8 A B C D E The Three-wire mode timing is shown in Figure 23-3 on page 140. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1. Referring to the timing diagram (Figure 23-3 on page 140), a bus transfer involves the following steps: 1. The Slave device and Master device sets up its data output and, depending on the protocol used, enables its output driver (mark A and B). The output is set up by writing the data to be transmitted to the Serial Data Register. Enabling of the output is done by setting the corresponding bit in the port Data Direction Register. Note that point A and B does not have any specific order, but both must be at least one half USCK cycle before point C where the data is sampled. This must be done to ensure that the data setup requirement is satisfied. The 4-bit counter is reset to zero. 2. The Master generates a clock pulse by software toggling the USCK line twice (C and D). The bit value on the slave and master's data input (DI) pin is sampled by the USI on the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter will count both edges. 3. Step 2 is repeated eight times for a complete register (byte) transfer. 4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer is completed. The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it is set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. 140 ATA8742 9151A-INDCO-07/09 ATA8742 23.3.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: out ldi out ldi out in sbrs rjmp in ret USIDR,r16 r16,(1< The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register. The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4): SPITransfer_Fast: out ldi ldi out out out out out out out out out out out out out out out USIDR,r16 r16,(1< 9151A-INDCO-07/09 out in ret USICR,r17 r16,USIDR 23.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi out ... SlaveSPITransfer: out ldi out in sbrs rjmp in ret USIDR,r16 r16,(1< The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO is configured as output and USCK pin is configured as input in the DDR Register. The value stored in register r16 prior to the function is called is transferred to the master device, and when the transfer is completed the data received from the Master is stored back into the r16 Register. Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set. 142 ATA8742 9151A-INDCO-07/09 ATA8742 23.3.4 Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 23-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDA SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDA SCL PORTxn MASTER Figure 23-4 on page 143 shows two USI units operating in Two-wire mode, one as Master and one as Slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the Master and Slave operation at this level, is the serial clock generation which is always done by the Master, and only the Slave uses the clock control unit. Clock generation must be implemented in software, but the shift operation is done automatically by both devices. Note that only clocking on negative edge for shifting data is of practical use in this mode. The slave can insert wait states at start or end of transfer by forcing the SCL clock low. This means that the Master must always check if the SCL line was actually released after it has generated a positive edge. Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. 143 9151A-INDCO-07/09 Figure 23-5. Two-wire Mode, Typical Timing Diagram SDA SCL S 1-7 ADDRESS 8 R/W 9 ACK 1-8 DATA 9 ACK 1-8 DATA 9 ACK P A B C D E F Referring to the timing diagram (Figure 23-5 on page 144), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the Data Direction Register bit must be set to one for the output to be enabled. The slave device's start detector logic (Figure 23-6 on page 144) detects the start condition and sets the USISIF Flag. The flag can generate an interrupt if necessary. 2. In addition, the start detector will hold the SCL line low after the Master has forced an negative edge on this line (B). This allows the Slave to wake up from sleep or complete its other tasks before setting up the Shift Register to receive the address. This is done by clearing the start condition flag and reset the counter. 3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave samples the data and shift it into the Serial Register at the positive edge of the SCL clock. 4. After eight bits are transferred containing slave address and data direction (read or write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not the one the Master has addressed, it releases the SCL line and waits for a new start condition. 5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle before holding the SCL line low again (i.e., the Counter Register must be set to 14 before releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its output. If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E). 6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the Master (F). Or a new start condition is given. If the Slave is not able to receive more data it does not acknowledge the data byte it has last received. When the Master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted. Figure 23-6. Start Condition Detector, Logic Diagram USISIF DQ SDA CLR CLR DQ CLOCK HOLD SCL Write( USISIF) 144 ATA8742 9151A-INDCO-07/09 ATA8742 23.3.5 Start Condition Detector The start condition detector is shown in Figure 23-6 on page 144. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by the CKSEL Fuses (see "Clock Systems and their Distribution" on page 41) must also be taken into the consideration. See the USISIF bit description in "USISR - USI Status Register" on page 146 for further details. 23.3.6 Clock speed considerations Maximum frequency for SCL and SCK is fCK /4. This is also the maximum data transmit and receive rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Control Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the actual data rate in two-wire mode. 23.4 Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. 23.4.1 Half-duplex Asynchronous Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only. 23.4.2 4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked externally, both clock edges will generate an increment. 23.4.3 12-bit Timer/Counter Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit counter. 23.4.4 Edge Triggered External Interrupt By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit. 23.4.5 Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 145 9151A-INDCO-07/09 23.5 23.5.1 Register Descriptions USIBR - USI Data Buffer Bit 0x10 (0x30) Read/Write Initial Value 7 MSB R 0 R 0 R 0 R 0 R 0 R 0 R 0 6 5 4 3 2 1 0 LSB R 0 USIBR 23.5.2 USIDR - USI Data Register Bit 0x0F (0x2F) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 USIDR The USI uses no buffering of the Serial Register, i.e., when accessing the Data Register (USIDR) the Serial Register is accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed. A (left) shift operation is performed depending of the USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note that even when no wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the Shift Register. The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) during the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The output will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges. Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the Shift Register. 23.5.3 USISR - USI Status Register Bit 0x0E (0x2E) Read/Write Initial Value 7 USISIF 6 USIOIF 5 USIPF 4 USIDC 3 USICNT3 2 USICNT2 1 USICNT1 0 USICNT0 USISR R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 The Status Register contains Interrupt Flags, line Status Flags and the counter value. * Bit 7 - USISIF: Start Condition Interrupt Flag When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag. 146 ATA8742 9151A-INDCO-07/09 ATA8742 An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode. A start condition interrupt will wake up the processor from all sleep modes. * Bit 6 - USIOIF: Counter Overflow Interrupt Flag This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global Interrupt Enable Flag are set. The flag is cleared if a one is written to the USIOIF bit or by reading the USIBR register. Clearing this bit will release the counter overflow hold of SCL in Two-wire mode. A counter overflow interrupt will wake up the processor from Idle sleep mode. * Bit 5 - USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is useful when implementing Two-wire bus master arbitration. * Bit 4 - USIDC: Data Output Collision This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The flag is only valid when Two-wire mode is used. This signal is useful when implementing Two-wire bus master arbitration. * Bits 3..0 - USICNT3..0: Counter Value These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1). Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input (USCK/SCL) are can still be used by the counter. 23.5.4 USICR - USI Control Register Bit 0x0D (0x2D) Read/Write Initial Value 7 USISIE R/W 0 6 USIOIE R/W 0 5 USIWM1 R/W 0 4 USIWM0 R/W 0 3 USICS1 R/W 0 2 USICS0 R/W 0 1 USICLK W 0 0 USITC W 0 USICR The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. * Bit 7 - USISIE: Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt. If there is a pending interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be 147 9151A-INDCO-07/09 executed. See the USISIF bit description in "USISR - USI Status Register" on page 146 for further details. * Bit 6 - USIOIE: Counter Overflow Interrupt Enable Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. See the USIOIF bit description in "USISR - USI Status Register" on page 146 for further details. * Bit 5..4 - USIWM1..0: Wire Mode These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1..0 and the USI operation is summarized in Table 23-1. Table 23-1. USIWM1 0 Relations between USIWM1..0 and the USI Operation USIWM0 0 Description Outputs, clock hold, and start detector disabled. Port pins operates as normal. Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit. The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port operation. When operating as master, clock pulses are software generated by toggling the PORT Register, while the data direction is set to output. The USITC bit in the USICR Register can be used for this purpose. Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1). The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and uses open-collector output drives. The output drivers are enabled by setting the corresponding bit for SDA and SCL in the DDR Register. When the output driver is enabled for the SDA pin, the output driver will force the line SDA low if the output of the Shift Register or the corresponding bit in the PORT Register is zero. Otherwise the SDA line will not be driven (i.e., it is released). When the SCL pin output driver is enabled the SCL line will be forced low if the corresponding bit in the PORT Register is zero, or by the start detector. Otherwise the SCL line will not be driven. The SCL line is held low when a start detector detects a start condition and the output is enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are disabled in Two-wire mode. Two-wire mode. Uses SDA and SCL pins. Same operation as for the Two-wire mode described above, except that the SCL line is also held low when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared. 0 1 1 0 1 1 Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation. 148 ATA8742 9151A-INDCO-07/09 ATA8742 * Bit 3..2 - USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1..0 bits enables software strobe option. When using this option, writing a one to the USICLK bit clocks both the Shift Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit. Table 23-2 on page 149 shows the relationship between the USICS1..0 and USICLK setting and clock source used for the Shift Register and the 4-bit counter. Table 23-2. USICS1 0 0 0 1 1 1 1 Relations between the USICS1..0 and USICLK Setting USICS0 0 0 1 0 1 0 1 USICLK 0 1 X 0 0 1 1 Shift Register Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, positive edge External, negative edge External, positive edge External, negative edge 4-bit Counter Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, both edges External, both edges Software clock strobe (USITC) Software clock strobe (USITC) * Bit 1 - USICLK: Clock Strobe Writing a one to this bit location strobes the Shift Register to shift one step and the counter to increment by one, provided that the USICS1..0 bits are set to zero and by doing so the software clock strobe option is selected. The output will change immediately when the clock strobe is executed, i.e., in the same instruction cycle. The value shifted into the Shift Register is sampled the previous instruction cycle. The bit will be read as zero. When an external clock source is selected (USICS1 = 1), the USICLK function is changed from a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4-bit counter (see Table 23-2 on page 149). * Bit 0 - USITC: Toggle Clock Port Pin Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0. The toggling is independent of the setting in the Data Direction Register, but if the PORT value is to be shown on the pin the DDRE4 must be set as output (to one). This feature allows easy clock generation when implementing master devices. The bit will be read as zero. When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. 149 9151A-INDCO-07/09 24. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 24-1 on page 150. Figure 24-1. Analog Comparator Block Diagram(1) BANDGAP REFERENCE ACBG ACME ADEN ADC MULTIPLEXER OUTPUT (1) Notes: 1. See Table 24-1 on page 151. 24.1 Analog Comparator Multiplexed Input When the Analog to Digital Converter (ADC) is configured as single ended input channel, it is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 24-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. 150 ATA8742 9151A-INDCO-07/09 ATA8742 Table 24-1. ACME 0 1 1 1 1 1 1 1 1 1 Analog Comparator Multiplexed Input ADEN x 1 0 0 0 0 0 0 0 0 MUX4..0 xx xx 00000 00001 00010 00011 00100 00101 00110 00111 Analog Comparator Negative Input AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 151 9151A-INDCO-07/09 24.2 24.2.1 Register Description ADCSRB - ADC Control and Status Register B Bit 0x03 (0x23) Read/Write Initial Value 7 BIN R/W 0 6 ACME R/W 0 5 - R 0 4 ADLAR R/w 0 3 - R 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB * Bit 6 - ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see "Analog Comparator Multiplexed Input" on page 150. 24.2.2 ACSR - Analog Comparator Control and Status Register Bit 0x08 (0x28) Read/Write Initial Value 7 ACD R/W 0 6 ACBG R/W 0 5 ACO R/W N/A 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR * Bit 7 - ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. * Bit 6 - ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. * Bit 5 - ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. * Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. 152 ATA8742 9151A-INDCO-07/09 ATA8742 * Bit 2 - ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-rupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. * Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 24-2. Table 24-2. ACIS1 0 0 1 1 ACIS1/ACIS0 Settings ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle. Reserved Comparator Interrupt on Falling Output Edge. Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 24.2.3 DIDR0 - Digital Input Disable Register 0 Bit 0x01 (0x21) Read/Write Initial Value 7 ADC7D R/W 0 6 ADC6D R/W 0 5 ADC5D R/W 0 4 ADC4D R/W 0 3 ADC3D R/W 0 2 ADC2D R/W 0 1 ADC1D R/W 0 0 ADC0D R/W 0 DIDR0 * Bits 1, 0 - ADC0D,ADC1D: ADC 1/0 Digital input buffer disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 153 9151A-INDCO-07/09 25. Analog to Digital Converter 25.1 Features * * * * * * * * * * * * * * * * * 10-bit Resolution 1.0 LSB Integral Non-linearity 2 LSB Absolute Accuracy 65 - 260 s Conversion Time Up to 76 kSPS at Maximum Resolution Eight Multiplexed Single Ended Input Channels Twelve differential input channels with selectable gain (1x, 20x) Temperature sensor input channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 1.1V ADC Reference Voltage Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler Unipolar / Bipolar Input Mode Input Polarity Reversal channels 25.2 Overview The ATtiny24/44/84 features a 10-bit successive approximation ADC. The ADC is connected to 8-pin port A for external sources. In addition to external sources internal temperature sensor can be measured by ADC. Analog Multiplexer allows eight single-ended channels or 12 differential channels from Port A. The programmable gain stage provides ampification steps 0 dB (1x) and 26 dB (20x) for 12 differential ADC channels. The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 25-1 on page 155. Internal reference voltage of nominally 1.1V is provided On-chip. Alternatively, VCC can be used as reference voltage for single ended channels. There is also an option to use an external voltage reference and turn-off the internal voltage reference. 154 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 25-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS2...ADTS0 8-BIT DATA BUS ADIF ADIE 15 ADC DATA REGISTER (ADCH/ADCL) ADC[9:0] 0 ADC CTRL. & STATUS B REGISTER (ADCSRB) BIN IPR ADC MULTIPLEXER SELECT (ADMUX) MUX4...MUX0 ADLAR ADEN ADC CTRL. & STATUS A REGISTER (ADCSRA) ADATE ADPS2 ADPS1 ADPS0 ADSC ADIF AREF REFS1..REFS0 TRIGGER SELECT MUX DECODER CHANNEL SELECTION PRESCALER GAIN SELECTION START VCC INTERNAL REFERENCE 1.1V TEMPERATURE SENSOR CONVERSION LOGIC SAMPLE & HOLD COMPARATOR 10-BIT DAC + ADC8 AGND ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 POS. INPUT MUX SINGLE ENDED / DIFFERENTIAL SELECTION ADC MULTIPLEXER OUTPUT + - GAIN AMPLIFIER NEG. INPUT MUX 25.3 ADC Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the reference voltage.The voltage reference for the ADC may be selected by writing to the REFS1..0 bits in ADMUX. The VCC supply, the AREF pin or an internal 1.1V voltage reference may be selected as the ADC voltage reference. The analog input channel and differential gain are selected by writing to the MUX5..0 bits in ADMUX. Any of the eight ADC input pins ADC7..0 can be selected as single ended inputs to the ADC. For differential measurements all analog inputs next to each other can be selected as a input pair. Every input is also possible to measure with ADC3. These pairs of differential inputs are measured by ADC trough the differential gain amplifier. If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor, 1x or 20x, according to the setting of 155 9151A-INDCO-07/09 the MUX0 bit in ADMUX. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The offset of the differential channels can be measure by selecting the same input for both negative and positive input. Offset calibration can be done for ADC0, ADC3 and ADC7. When ADC0 or ADC3 or ADC7 is selected as both the positive and negative input to the differential gain amplifier, the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. This figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 LSB. The on-chip temperature sensor is selected by writing the code "100010" to the MUX5..0 bits in ADMUX register. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADCSRB. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. 25.4 Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. 156 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 25-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF SOURCE 1 . . . . SOURCE n ADSC ADATE CLKADC CONVERSION LOGIC EDGE DETECTOR Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 25.5 Prescaling and Conversion Timing Figure 25-3. ADC Prescaler ADEN START CK Reset 7-BIT ADC PRESCALER ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. CK/128 CK/16 CK/32 CK/64 CK/2 CK/4 CK/8 157 9151A-INDCO-07/09 The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 25-1 on page 159. Figure 25-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) First Conversion Next Conversion Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result MUX and REFS Update Sample & Hold Conversion Complete MUX and REFS Update Figure 25-5. ADC Timing Diagram, Single Conversion One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete MUX and REFS Update 158 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 25-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Next Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete Prescaler Reset Prescaler Reset Figure 25-7. ADC Timing Diagram, Free Running Conversion One Conversion 11 12 13 Next Conversion 1 2 3 4 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result Conversion Complete Sample & Hold MUX and REFS Update Table 25-1. Condition ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) 14.5 1.5 2 Conversion Time (Cycles) 25 13 13.5 First conversion Normal conversions Auto Triggered conversions 159 9151A-INDCO-07/09 25.6 Changing Channel or Reference Selection The MUX5:0 and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: a. When ADATE or ADEN is cleared. b. c. During conversion, minimum one ADC clock cycle after the trigger event. After a conversion, before the Interrupt Flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. 25.6.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 25.6.2 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V reference, or external AREF pin. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 160 ATA8742 9151A-INDCO-07/09 ATA8742 25.7 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: a. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. b. c. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 25.7.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 25-8 on page 161. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10 k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fADC/2) should not be present to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 25-8. Analog Input Circuitry IIH ADCn 1..100 k CS/H= 14 pF IIL VCC/2 161 9151A-INDCO-07/09 25.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. c. Use the ADC noise canceler function to reduce induced noise from the CPU. If any port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. 25.7.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: * Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 25-9. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage * Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB 162 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 25-10. Gain Error Output Code Gain Error Ideal ADC Actual ADC VREF Input Voltage * Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 25-11. Integral Non-linearity (INL) Output Code * Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. INL Ideal ADC Actual ADC VREF Input Voltage 163 9151A-INDCO-07/09 Figure 25-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage * Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB. * Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: 0.5 LSB. 25.8 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). The form of the conversion result depends on the type of the conversion as there are three types of conversions: single ended conversion, unipolar differential conversion and bipolar differential conversion. 25.8.1 Single Ended Conversion For single ended conversion, the result is V IN 1024 ADC = ---------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 25-3 on page 166 and Table 25-4 on page 167). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. The result is presented in one-sided form, from 0x3FF to 0x000. 25.8.2 Unipolar Differential Conversion If differential channels and an unipolar input mode are used, the result is ( V POS - V NEG ) 1024 ADC = ---------------------------------------------------------- GAIN V REF where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference. The voltage of the positive pin must always be larger 164 ATA8742 9151A-INDCO-07/09 ATA8742 than the voltage of the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from 0x000 (0d) through 0x3FF (+1023d). The GAIN is either 1x or 20x. 25.8.3 Bipolar Differential Conversion If differential channels and a bipolar input mode are used, the result is ( V POS - V NEG ) 512 ADC = ------------------------------------------------------- GAIN V REF where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference. The result is presented in two's complement form, from 0x200 (-512d) through 0x1FF (+511d). The GAIN is either 1x or 20x. Note that if the user wants to perform a quick polarity check of the result, it is sufficient to read the MSB of the result (ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is positive. As default the ADC converter operates in the unipolar input mode, but the bipolar input mode can be selected by writing the BIN bit in the ADCSRB to one. In the bipolar input mode two-sided voltage differences are allowed and thus the voltage on the negative input pin can also be larger than the voltage on the positive input pin. 25.9 Temperature Measurement The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC8 channel. Selecting the ADC8 channel by writing the MUX5:0 bits in ADMUX register to "100010" enables the temperature sensor. The internal 1.1V reference must also be selected for the ADC reference source in the temperature sensor measurement. When the temperature sensor is enabled, the ADC converter can be used in single conversion mode to measure the voltage over the temperature sensor. The measured voltage has a linear relationship to the temperature as described in Table 51. The voltage sensitivity is approximately 1 mV / C and the accuracy of the temperature measurement is +/- 10C after offset calibration. Bandgap is always calibrated and its accuracy is only guaranteed between 1.0V and 1.2V Table 25-2. Temperature vs. Sensor Output Voltage (Typical Case) -40C 243 mV +25C 314 mv +85C 380 mV +125C 424 mV Temperature / C Voltage / mV The values described in Table 25-2 on page 165 are typical values. However, due to the process variation the temperature sensor output voltage varies from one chip to another. To be capable of achieving more accurate results the temperature measurement can be calibrated in the application software. The software calibration requires that a calibration value is measured and stored in a register or EEPROM for each chip, as a part of the production test. The software calibration can be done utilizing the formula: T = {[(ADCH << 8) | ADCL] - TOS} / k where ADCn are the ADC data registers, k is a fixed coefficient and TOS is the temperature sensor offset value determined and stored into EEPROM as a part of the production test.To obtain best accuracy the coefficient k should be measured using two temperature calibrations. Using offset calibration, set k = 1.0, where k = (1024*1.07mV/C)/1.1V~1.0 [1/C]. 165 9151A-INDCO-07/09 25.10 Register Description 25.10.1 ADMUX - ADC Multiplexer Selection Register Bit 0x07 (0x27) Read/Write Initial Value 7 REFS1 R/W 0 6 REFS0 R/W 0 5 MUX5 R/W 0 4 MUX4 R/W 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX * Bit 7:6 - REFS1:REFS0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 25-3 on page 166. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). Special care should be taken when changing differential channels. Once a differential channel has been selected, the stage may take as much as 25 ADC clock cycles to stabilize to the new value. Thus conversions should not be started within the first 13 clock cycles after selecting a new differential channel. Alternatively, conversion results obtained within this period should be discarded. The same settling time should be observed for the first differential conversion after changing ADC reference (by changing the REFS1:0 bits in ADMUX). If channels where differential gain is used ie. the gainstage, using VCC or an optional external AREF higher than (VCC - 1V) is not recommended, as this will affect ADC accuracy. It is not allowed to connect internal voltage reference to AREF pin, if an external voltage is being applied to it already. Internal voltage reference is connected AREF pin when REFS1:0 is set to value `11'. Table 25-3. REFS1 0 0 1 1 Voltage Reference Selections for ADC REFS0 0 1 0 1 Voltage Reference Selection VCC used as analog reference, disconnected from PA0 (AREF). External Voltage Reference at PA0 (AREF) pin, Internal Voltage Reference turned off. Internal 1.1V Voltage Reference. Reserved. * Bits 5:0 - MUX5:0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. In case of differential input, gain selection is also made with these bits. Selections on Table 25-4 on page 167 show values for single ended channels and where the differential channels as well as the offset calibration selections are located. Selecting the single-ended channel ADC8 enables the temperature measurement. See Table 25-4 on page 167 for details. If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set). 166 ATA8742 9151A-INDCO-07/09 ATA8742 Table 25-4. Single Ended Input channel Selections. Single Ended Input ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC4 (PA4) ADC5 (PA5) ADC6 (PA6) ADC7 (PA7) Reserved for differential channels 0V (AGND) 1.1V (I Ref) ADC8 (2) (3) (1) MUX5..0 000000 000001 000010 000011 000100 000101 000110 000111 001000 - 011111 100000 100001 100010 100011 - 100111 101000 - 111111 Reserved for offset calibration Reserved for reversal differential channels(1) Notes: 1. See Table 25-5 on page 168 for details. 2. "Temperature Measurement" on page 165 3. For offset calibration only .See Table 25-5 on page 168 and "ADC Operation" on page 155 See Table 25-5 on page 168 for details of selections of differential input channel selections as well as selections of offset calibration channels. MUX0 bit works as a gain selection bit for differential channels shown in Table 25-5 on page 168. When MUX0 bit is cleared (`0') 1x gain is selected and when it is set (`1') 20x gain is selected. For normal differential channel pairs MUX5 bit work as a polarity reversal bit. Togling of the MUX5 bit exchanges the positive and negative channel other way a round. For offset calibration purpose the offset of the certain differential channels can be measure by selecting the same input for both negative and positive input. This calibration can be done for ADC0, ADC3 and ADC7. "ADC Operation" on page 155 describes offset calibration in a more detailed level. 167 9151A-INDCO-07/09 Table 25-5. Differential Input channel Selections. Negative Differential Input ADC0 (PA0) (1) MUX5.0 Gain 1x N/A 001000 001010 101000 001100 001110 101100 010000 101010 101110 110000 100100 010010 010100 010110 011000 110010 011010 110100 111010 011100 110110 111100 011110 111000 111110 100110 Gain 20x 100011 001001 001011 101001 001101 001111 101101 010001 101011 101111 110001 100101 010011 010101 010111 011001 110011 011011 110101 111011 011101 110111 111101 011111 111001 111111 100111 Positive Differential Input ADC0 (PA0) ADC1 (PA1) ADC3 (PA3) ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC3 (PA3) ADC4 (PA4 ADC5 (PA5) ADC6 (PA6) ADC7 (PA7) ADC3 (PA3) ADC4 (PA4 ADC5 (PA5) ADC3 (PA3) ADC5 (PA5) ADC4 (PA4) ADC6 (PA6) ADC3 (PA3) ADC6 (PA6) ADC5 (PA5) ADC7 (PA7) ADC3 (PA3) ADC7 (PA7) ADC6 (PA6) ADC7 (PA7) 1. (1) (1) For offset calibration only.See "ADC Operation" on page 155 168 ATA8742 9151A-INDCO-07/09 ATA8742 25.10.2 ADCSRA - ADC Control and Status Register A Bit 0x06 (0x26) Read/Write Initial Value 7 ADEN R/W 0 6 ADSC R/W 0 5 ADATE R/W 0 4 ADIF R/W 0 3 ADIE R/W 0 2 ADPS2 R/W 0 1 ADPS1 R/W 0 0 ADPS0 R/W 0 ADCSRA * Bit 7 - ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. * Bit 6 - ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. * Bit 5 - ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. * Bit 4 - ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI instruction is used. * Bit 3 - ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. * Bits 2:0 - ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 25-6. ADPS2 0 0 0 0 1 ADC Prescaler Selections ADPS1 0 0 1 1 0 ADPS0 0 1 0 1 0 Division Factor 2 2 4 8 16 169 9151A-INDCO-07/09 Table 25-6. ADPS2 1 1 1 ADC Prescaler Selections (Continued) ADPS1 0 1 1 ADPS0 1 0 1 Division Factor 32 64 128 25.10.3 25.10.3.1 ADCL and ADCH - ADC Data Register ADLAR = 0 Bit 0x05 (0x25) 0x04 (0x24) 15 - ADC7 7 Read/Write R R Initial Value 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL 25.10.3.2 ADLAR = 1 Bit 0x05 (0x25) 0x04 (0x24) 15 ADC9 ADC1 7 Read/Write R R Initial Value 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. * ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in "ADC Conversion Result" on page 164. 170 ATA8742 9151A-INDCO-07/09 ATA8742 25.10.4 ADCSRB - ADC Control and Status Register B Bit 0x03 (0x23) Read/Write Initial Value 7 BIN R/W 0 6 ACME R/W 0 5 - R/W 0 4 ADLAR R/W 0 3 - R/W 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB * Bits 7 - BIN: Bipolar Input Mode The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions are supported and the voltage on the positive input must always be larger than the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode two-sided conversions are supported and the result is represented in the two's complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. * Bit 6 - ACME: Analog Comparator Multiplexer Enable See "ADCSRB - ADC Control and Status Register B" on page 152. * Bit 5 - Res: Reserved Bit This bit is reserved bit in the ATtiny24/44/84 and will always read as what was wrote there. * Bit 4 - ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see "ADCL and ADCH - ADC Data Register" on page 170. * Bit 3 - Res: Reserved Bit This bit is reserved bit in the ATtiny24/44/84 and will always read as what was wrote there. * Bits 2:0 - ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 25-7. ADTS2 0 0 0 0 1 ADC Auto Trigger Source Selections ADTS1 0 0 1 1 0 ADTS0 0 1 0 1 0 Trigger Source Free Running mode Analog Comparator External Interrupt Request 0 Timer/Counter0 Compare Match A Timer/Counter0 Overflow 171 9151A-INDCO-07/09 Table 25-7. ADTS2 1 1 1 ADC Auto Trigger Source Selections ADTS1 0 1 1 ADTS0 1 0 1 Trigger Source Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter1 Capture Event 25.10.5 DIDR0 - Digital Input Disable Register 0 Bit 0x01 (0x21) Read/Write Initial Value 7 ADC7D R/W 0 6 ADC6D R/W 0 5 ADC5D R/W 0 4 ADC4D R/W 0 3 ADC3D R/W 0 2 ADC2D R/W 0 1 ADC1D R/W 0 0 ADC0D R/W 0 DIDR0 * Bits 7..0 - ADC7D..ADC0D: ADC7..0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 172 ATA8742 9151A-INDCO-07/09 ATA8742 26. debugWIRE On-chip Debug System 26.1 Features * * * * * * * * * * Complete Program Flow Control Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin Real-time Operation Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs) Unlimited Number of Program Break Points (Using Software Break Points) Non-intrusive Operation Electrical Characteristics Identical to Real Device Automatic Configuration System High-Speed Operation Programming of Non-volatile Memories 26.2 Overview The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, execute AVR instructions in the CPU and to program the different non-volatile memories. 26.3 Physical Interface When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. Figure 26-1. The debugWIRE Setup 1.8 - 5.5V VCC dW dW(RESET) GND Figure 26-1 on page 173 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. 173 9151A-INDCO-07/09 When designing a system where debugWIRE will be used, the following observations must be made for correct operation: * Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 k. However, the pull-up resistor is optional. * Connecting the RESET pin directly to VCC will not work. * Capacitors inserted on the RESET pin must be disconnected when using debugWire. * All external reset sources must be disconnected. 26.4 Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR Studio(R) will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing from the Program memory. A break can be inserted manually by putting the BREAK instruction in the program. The Flash must be re-programmed each time a Break Point is changed. This is automatically handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore reduce the Flash Data retention. Devices used for debugging purposes should not be shipped to end customers. 26.5 Limitations of debugWIRE The debugWIRE communication pin (dW) is physically located on the same pin as External Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is enabled. The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e., when the program in the CPU is running. When the CPU is stopped, care must be taken while accessing some of the I/O Registers via the debugger (AVR Studio). See the debugWIRE documentation for detailed description of the limitations. A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not used. 26.6 Register Description The following section describes the registers used with the debugWire. 26.6.1 DWDR - debugWire Data Register Bit 0x27 (0x47) Read/Write Initial Value 7 6 5 4 3 2 1 0 DWDR DWDR[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. 174 ATA8742 9151A-INDCO-07/09 ATA8742 27. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation: Alternative 1, fill the buffer before a Page Erase * Fill temporary page buffer * Perform a Page Erase * Perform a Page Write Alternative 2, fill the buffer after Page Erase * Perform a Page Erase * Fill temporary page buffer * Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re-written. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. 27.0.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write "00000011" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. * The CPU is halted during the Page Erase operation. 27.0.2 Filling the Temporary Buffer (Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write "00000001" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 175 9151A-INDCO-07/09 27.0.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write "00000101" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. * The CPU is halted during the Page Write operation. 27.1 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0 Since the Flash is organized in pages (see Table 28-7 on page 183), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in Figure 28-1 on page 184. Note that the Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that the software addresses the same page in both the Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 27-1. Addressing the Flash During SPM(1) BIT Z - REGISTER PCMSB PROGRAM COUNTER PCPAGE 15 ZPCMSB ZPAGEMSB 10 0 PAGEMSB PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 1. The different variables used in Figure 27-1 are listed in Table 28-7 on page 183. 176 ATA8742 9151A-INDCO-07/09 ATA8742 27.1.1 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 27.1.2 Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When RFLB and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Bit Rd 7 - 6 - 5 - 4 - 3 - 2 - 1 LB2 0 LB1 The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. See Table 28-5 on page 182 for a detailed description and mapping of the Fuse Low byte. Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0 Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. See Table 28-4 on page 181 for detailed description and mapping of the Fuse High byte. Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. 27.1.3 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. 177 9151A-INDCO-07/09 Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 27.1.4 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 27-1 shows the typical programming time for Flash accesses from the CPU. Table 27-1. SPM Programming Time(1) Symbol Flash write (Page Erase, Page Write, and write Lock bits by SPM) Note: Min Programming Time 3.7 ms Max Programming Time 4.5 ms 1. The min and max programming times is per individual operation. 27.2 27.2.1 Register Description SPMCSR - Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations. Bit 0x37 (0x57) Read/Write Initial Value 7 - 6 - 5 - 4 CTPB 3 RFLB 2 PGWRT 1 PGERS 0 SPMEN SPMCSR R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 * Bits 7..5 - Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and always read as zero. * Bit 4 - CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. * Bit 3 - RFLB: Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See "EEPROM Write Prevents Writing to SPMCSR" on page 177 for details. * Bit 2 - PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit 178 ATA8742 9151A-INDCO-07/09 ATA8742 will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. * Bit 1 - PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. * Bit 0 - SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than "10001", "01001", "00101", "00011" or "00001" in the lower five bits will have no effect. 179 9151A-INDCO-07/09 28. Memory Programming This section describes the different methods for Programming the ATtiny24/44/84 memories. 28.1 Program And Data Memory Lock Bits The ATtiny24/44/84 provides two Lock bits which can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional security listed in Table 28-2 on page 180. The Lock bits can only be erased to "1" with the Chip Erase command. Program memory can be read out via the debugWIRE interface when the DWEN fuse is programmed, even if the Lock Bits are set. Thus, when Lock Bit security is required, should always debugWIRE be disabled by clearing the DWEN fuse. Table 28-1. Lock Bit Byte(1) Bit No 7 6 5 4 3 2 LB2 LB1 Note: 1 0 Description - - - - - - Lock bit Lock bit Default Value 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) Lock Bit Byte 1. "1" means unprogrammed, "0" means programmed Table 28-2. Lock Bit Protection Modes(1)(2) Protection Type LB1 1 No memory lock features enabled. Further programming of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode. The Fuse bits are locked in both Serial and High-voltage Programming mode.(1) debugWire is disabled. Further programming and verification of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode. The Fuse bits are locked in both Serial and High-voltage Programming mode.(1) debugWire is disabled. Memory Lock Bits LB Mode 1 LB2 1 2 1 0 3 0 0 Notes: 1. Program the Fuse bits before programming the LB1 and LB2. 2. "1" means unprogrammed, "0" means programmed 180 ATA8742 9151A-INDCO-07/09 ATA8742 28.2 Fuse Bytes The ATtiny24/44/84 has three Fuse bytes. Table 28-4 on page 181 to Table 28-5 on page 182 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, "0", if they are programmed.. Table 28-3. Fuse Extended Byte Bit No 7 6 5 4 3 2 1 SELFPRGEN 0 Description Self-Programming Enable Default Value 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) Fuse High Byte Table 28-4. (1) Fuse High Byte Bit No 7 6 6 4 3 2 1 0 Description External Reset disable DebugWIRE Enable Enable Serial Program and Data Downloading Watchdog Timer always on EEPROM memory is preserved through the Chip Erase Brown-out Detector trigger level Brown-out Detector trigger level Brown-out Detector trigger level Default Value 1 (unprogrammed) 1 (unprogrammed) 0 (programmed, SPI prog. enabled) 1 (unprogrammed) 1 (unprogrammed, EEPROM not preserved) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) Fuse High Byte RSTDISBL DWEN (2) SPIEN(3) WDTON(4) EESAVE BODLEVEL2(5) BODLEVEL1 BODLEVEL0 Notes: (5) (5) 1. See "Alternate Functions of Port B" on page 84 for description of RSTDISBL and DWEN Fuses. When programming the RSTDISBL Fuse, High-voltage Serial programming has to be used to change fuses to perform further programming 2. DWEN must be unprogrammed when Lock Bit security is required. See "Program And Data Memory Lock Bits" on page 180. 3. The SPIEN Fuse is not accessible in SPI Programming mode. 4. See "WDT Configuration as a Function of the Fuse Settings of WDTON" on page 60 for details. 5. See Table 29-5 on page 198 for BODLEVEL Fuse decoding. 181 9151A-INDCO-07/09 Table 28-5. CKDIV8(1) CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: Fuse Low Byte Bit No 7 6 5 4 3 2 1 0 Description Divide clock by 8 Clock Output Enable Select start-up time Select start-up time Select Clock source Select Clock source Select Clock source Select Clock source Default Value 0 (programmed) 1 (unprogrammed) 1 (unprogrammed)(2) 0 (programmed)(2) 0 (programmed)(3) 0 (programmed)(3) 1 (unprogrammed)(3) 0 (programmed)(3) Fuse Low Byte 1. See "System Clock Prescaler" on page 47 for details. 2. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 14-7 on page 45 for details. 3. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8.0 MHz. See Table 14-6 on page 45 for details. The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. 28.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 28.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and High-voltage Programming mode, also when the device is locked. The three bytes reside in a separate address space. For the ATtiny24/44/84 the signature bytes are given in Table 28-6. Table 28-6. Device ID Signature Bytes Address Parts ATtiny24 ATtiny44 ATtiny84 0x000 0x1E 0x1E 0x1E 0x001 0x91 0x92 0x93 0x002 0x0B 0x07 0x0C 28.4 Calibration Byte Signature area of the ATtiny24/44/84 has one byte of calibration data for the internal RC Oscillator. This byte resides in the high byte of address 0x000. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. 182 ATA8742 9151A-INDCO-07/09 ATA8742 28.5 Page Size Table 28-7. Device ATtiny24 ATtiny44 ATtiny84 No. of Words in a Page and No. of Pages in the Flash Flash Size 1K words (2K bytes) 2K words (4K bytes) 4K words (8K bytes) Page Size 16 words 32 words 32 words PCWORD PC[3:0] PC[4:0] PC[4:0] No. of Pages 64 64 128 PCPAGE PC[9:4] PC[10:5] PC[11:5] PCMSB 9 10 11 Table 28-8. Device ATtiny24 ATtiny44 ATtiny84 No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size 128 bytes 256 bytes 512 bytes Page Size 4 bytes 4 bytes 4 bytes PCWORD EEA[1:0] EEA[1:0] EEA[1:0] No. of Pages 32 64 128 PCPAGE EEA[6:2] EEA[7:2] EEA[8:2] EEAMSB 6 7 8 183 9151A-INDCO-07/09 28.6 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 28-9 on page 184, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. Figure 28-1. Serial Programming and Verify(1) +1.8 - 5.5V VCC MOSI MISO SCK RESET GND Note: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the CLKI pin. Table 28-9. Pin Mapping Serial Programming Pins PA6 PA5 PA4 I/O I O I Description Serial Data in Serial Data out Serial Clock Symbol MOSI MISO SCK When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 184 ATA8742 9151A-INDCO-07/09 ATA8742 28.6.1 Serial Programming Algorithm When writing serial data to the ATtiny24/44/84, data is clocked on the rising edge of SCK. When reading data from the ATtiny24/44/84, data is clocked on the falling edge of SCK. See Figure 29-3 and Figure 29-4 for timing details. To program and verify the ATtiny24/44/84 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 28-11): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 3 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 28-10 on page 186.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 28-10 on page 186.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table 28-10 on page 186). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. 185 9151A-INDCO-07/09 Table 28-10. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol tWD_FLASH tWD_EEPROM tWD_ERASE tWD_FUSE Minimum Wait Delay 4.5 ms 4.0 ms 4.0 ms 4.5 ms 28.6.2 Serial Programming Instruction set Table 28-11 on page 186 and Figure 28-2 on page 187 describes the Instruction set. Table 28-11. Serial Programming Instruction Set Instruction Format Instruction/Operation Programming Enable Chip Erase (Program Memory/EEPROM) Poll RDY/BSY Load Instructions Load Extended Address byte Load Program Memory Page, High byte Load Program Memory Page, Low byte Load EEPROM Memory Page (page access) Read Instructions Read Program Memory, High byte Read Program Memory, Low byte Read EEPROM Memory Read Lock bits Read Signature Byte Read Fuse bits Read Fuse High bits Read Extended Fuse Bits Read Calibration Byte Write Instructions(6) Write Program Memory Page Write EEPROM Memory Write EEPROM Memory Page (page access) Write Lock bits $4C $C0 $C2 $AC adr MSB $00 $00 $E0 adr LSB adr LSB adr LSB $00 $00 data byte in $00 data byte in $28 $20 $A0 $58 $30 $50 $58 $50 $38 adr MSB adr MSB $00 $00 $00 $00 $08 $08 $00 adr LSB adr LSB adr LSB $00 adr LSB $00 $00 $00 $00 high data byte out low data byte out data byte out data byte out data byte out data byte out data byte out data byte out data byte out $4D $48 $40 $C1 $00 adr MSB adr MSB $00 Extended adr adr LSB adr LSB adr LSB $00 high data byte in low data byte in data byte in (1) Byte 1 $AC $AC $F0 Byte 2 $53 $80 $00 Byte 3 $00 $00 $00 Byte4 $00 $00 data byte out 186 ATA8742 9151A-INDCO-07/09 ATA8742 Table 28-11. Serial Programming Instruction Set (Continued) Instruction Format Instruction/Operation(1) Write Fuse bits Write Fuse High bits Write Extended Fuse Bits Notes: 1. 2. 3. 4. 5. 6. 7. Byte 1 $AC $AC $AC Byte 2 $A0 $A8 $A4 Byte 3 $00 $00 $00 Byte4 data byte in data byte in data byte in Not all instructions are applicable for all parts. a = address Bits are programmed `0', unprogrammed `1'. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (`1') . Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size. Instructions accessing program memory use a word address. This address may be random within the page range. See http://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is `1', a programming operation is still pending. Wait until this bit returns `0' before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 28-2 on page 187. Figure 28-2. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 2 A Adr MSB Bit 15 B Byte 3 Adr LSB 0 Byte 4 Byte 1 Byte 2 Adr MSB Bit 15 B Byte 3 Adr LSB r B 0 Byte 4 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 187 9151A-INDCO-07/09 28.7 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATtiny24/44/84. Figure 28-3. High-voltage Serial Programming +11.5 - 12.5V PB3 (RESET) SCI +1.8 - 5.5V VCC PA4 SDO PB0 PA5 SII GND PA6 SDI Table 28-12. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode SDI SII SDO SCI Pin Name PA6 PA5 PA4 PB0 I/O I I O I Function Serial Data Input Serial Instruction Input Serial Data Output Serial Clock Input (min. 220ns period) The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is 220 ns. Table 28-13. Pin Values Used to Enter Programming Mode Pin PA0 PA1 PA2 Symbol Prog_enable[0] Prog_enable[1] Prog_enable[2] Value 0 0 0 188 ATA8742 9151A-INDCO-07/09 ATA8742 28.8 High-voltage Serial Programming Algorithm To program and verify the ATtiny24/44/84 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 28-15 on page 192): 28.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET pin to "0" and toggle SCI at least six times. 3. Set the Prog_enable pins listed in Table 28-13 on page 188 to "000" and wait at least 100 ns. 4. Apply VHVRST - 5.5V to RESET. Keep the Prog_enable pins unchanged for at least tHVRST after the High-voltage has been applied to ensure the Prog_enable signature has been latched. 5. Shortly after latching the Prog_enable signature, the device will actively output data on the Prog_enable[2]/SDO pin, and the resulting drive contention may increase the power consumption. To minimize this drive contention, release the Prog_enable[2] pin after tHVRST has elapsed. 6. Wait at least 50 s before giving any serial instructions on SDI/SII. Table 28-14. High-voltage Reset Characteristics Supply Voltage VCC 4.5V 5.5V RESET Pin High-voltage Threshold VHVRST 11.5V 11.5V Minimum High-voltage Period for Latching Prog_enable tHVRST 100 ns 100 ns 28.8.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. * The command needs only be loaded once when writing or reading multiple memory locations. * Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. * Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 28.8.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are re-programmed. Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. 1. Load command "Chip Erase" (see Table 28-15 on page 192). 2. Wait after Instr. 3 until SDO goes high for the "Chip Erase" cycle to finish. 3. Load Command "No Operation". 189 9151A-INDCO-07/09 28.8.4 Programming the Flash The Flash is organized in pages, see "Page Size" on page 183. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: 1. Load Command "Write Flash" (see Table 28-15 on page 192). 2. Load Flash Page Buffer. 3. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes high for the "Page Programming" cycle to finish. 4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command "No Operation". When writing or reading serial data to the ATtiny24/44/84, data is clocked on the rising edge of the serial clock, see Figure 29-5 on page 202, Figure 28-3 on page 188 and Table 29-9 on page 202 for details. Figure 28-4. Addressing the Flash which is Organized in Pages PCMSB PROGRAM COUNTER PCPAGE PAGEMSB PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Figure 28-5. High-voltage Serial Programming Waveforms SDI PB0 MSB LSB SII PB1 MSB LSB SDO PB2 MSB LSB SCI PB3 0 1 2 3 4 5 6 7 8 9 10 190 ATA8742 9151A-INDCO-07/09 ATA8742 28.8.5 Programming the EEPROM The EEPROM is organized in pages, see Table 29-8 on page 202. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 28-15 on page 192): 1. Load Command "Write EEPROM". 2. Load EEPROM Page Buffer. 3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the "Page Programming" cycle to finish. 4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been programmed. 5. End Page Programming by Loading Command "No Operation". 28.8.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to Table 28-15 on page 192): 1. Load Command "Read Flash". 2. Read Flash Low and High Bytes. The contents at the selected address are available at serial output SDO. 28.8.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Table 28-15 on page 192): 1. Load Command "Read EEPROM". 2. Read EEPROM Byte. The contents at the selected address are available at serial output SDO. 28.8.8 Programming and Reading the Fuse and Lock Bits The algorithms for programming and reading the Fuse Low/High bits and Lock bits are shown in Table 28-15 on page 192. 28.8.9 Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in Table 28-15 on page 192. 28.8.10 Power-off sequence Set SCI to "0". Set RESET to "1". Turn VCC power off. 191 9151A-INDCO-07/09 Table 28-15. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 Instruction Format Instruction SDI Chip Erase SII SDO Load "Write Flash" Command SDI SII SDO SDI SII Load Flash Page Buffer SDO SDI SII SDO Instr.1/5 0_1000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0001_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_ bbbb_bbbb _00 0_0000_1100_00 x_xxxx_xxxx_xx 0_dddd_dddd_00 0_0011_1100_00 x_xxxx_xxxx_xx Instr.2/6 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx Instr.3/7 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Instr.4 Operation Remarks Wait after Instr.3 until SDO goes high for the Chip Erase cycle to finish. Enter Flash Programming code. 0_eeee_eeee_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1101_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1101_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Repeat after Instr. 1 - 7until the entire page buffer is filled or until all data within the page is filled. See Note 1. Instr 5-7. Load Flash High Address and Program Page SDI SII SDO 0_0000_000a_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait after Instr 3 until SDO goes high. Repeat Instr. 2 - 3 for each loaded Flash Page until the entire Flash or all data is programmed. Repeat Instr. 1 for a new 256 byte page. See Note 1. Load "Read Flash" Command SDI SII SDO SDI SII 0_0000_0010_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0001_0001_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Wait after Instr. 2 until SDO goes high. Repeat Instr. 1 - 2 for each loaded EEPROM page until the entire EEPROM or all data is programmed. 0_aaaa_aaaa_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_eeee_eeee_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1101_00 x_xxxx_xxxx_xx 0_0000_000a_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 p_pppp_pppx_xx Enter EEPROM Programming mode. Repeat Instr. 1 - 5 until the entire page buffer is filled or until all data within the page is filled. See Note 2. Instr 5 - 6. 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 q_qqqq_qqqx_xx Repeat Instr. 1, 3 - 6 for each new address. Repeat Instr. 2 for a new 256 byte page. Enter Flash Read mode. Read Flash Low and High Bytes SDO SDI SII SDO Load "Write EEPROM" Command SDI SII SDO SDI SII Load EEPROM Page Buffer SDO SDI SII SDO Program EEPROM Page SDI SII SDO 192 ATA8742 9151A-INDCO-07/09 ATA8742 Table 28-15. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Format Instruction SDI SII Write EEPROM Byte SDO SDI SII SDO Load "Read EEPROM" Command Read EEPROM Byte Write Fuse Low Bits SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO SDI SII SDO Instr.1/5 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0011_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0100_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0010_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0100_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0100_1100_00 x_xxxx_xxxx_xx Instr.2/6 0_aaaa_aaaa_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Instr.3/7 0_eeee_eeee_00 0_0010_1100_00 x_xxxx_xxxx_xx Instr.4 0_0000_0000_00 0_0110_1101_00 x_xxxx_xxxx_xx Operation Remarks Repeat Instr. 1 - 6 for each new address. Wait after Instr. 6 until SDO goes high. See Note 3. Instr. 5-6 Enter EEPROM Read mode. 0_aaaa_aaaa_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_A987_6543_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_IHGF_EDCB_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_000J_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0021_00 0_0010_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1010_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1010_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_00bb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0110_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 A_9876_543x_xx 0_0000_0000_00 0_0111_1100_00 I_HGFE_DCBx_xx 0_0000_0000_00 0_0110_1110_00 x_xxxx_xxJx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_x21x_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 q_qqqq_qqq0_00 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1110_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1100_00 x_xxxx_xxxx_xx Repeat Instr. 1, 3 - 4 for each new address. Repeat Instr. 2 for a new 256 byte page. Wait after Instr. 4 until SDO goes high. Write A - 3 = "0" to program the Fuse bit. Wait after Instr. 4 until SDO goes high. Write F - B = "0" to program the Fuse bit. Wait after Instr. 4 until SDO goes high. Write J = "0" to program the Fuse bit. Wait after Instr. 4 until SDO goes high. Write 2 - 1 = "0" to program the Lock Bit. Reading A - 3 = "0" means the Fuse bit is programmed. Write Fuse High Bits Write Fuse Extended Bits Write Lock Bits Read Fuse Low Bits Read Fuse High Bits Reading F - B = "0" means the Fuse bit is programmed. Read Fuse Extended Bits Reading J = "0" means the Fuse bit is programmed. Read Lock Bits Read Signature Bytes Read Calibration Byte Load "No Operation" Command Reading 2, 1 = "0" means the Lock bit is programmed. 0_0000_0000_00 0_0110_1100_00 q_qqqq_qqqx_xx 0_0000_0000_00 0_0111_1100_00 p_pppp_pppx_xx Repeats Instr 2 4 for each signature byte address. 193 9151A-INDCO-07/09 Note: a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits, x = don't care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = CKSEL2 Fuse, 6 = CKSEL3 Fuse, 7 = SUT0 Fuse, 8 = SUT1 Fuse, 9 = CKDIV8 Fuse, A = CKOUT Fuse, B = BODLEVEL0 Fuse, C = BODLEVEL1 Fuse, D= BODLEVEL2 Fuse, E = EESAVE Fuse, F = WDTON Fuse, G = SPIEN Fuse, H = DWEN Fuse, I = RSTDISBL Fuse 1. For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address. 2. For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address. 3. The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM. Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming. Notes: 194 ATA8742 9151A-INDCO-07/09 ATA8742 29. Electrical Characteristics 29.1 Absolute Maximum Ratings *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Automotive Operating Temperature ..............- 40C to +125C Storage Temperature ....................................- 65C to +150C Voltage on any Pin except RESET with respect to Ground .............................. - 0.5V to VCC+0.5V Voltage on RESET with respect to Ground.... - 0.5V to +13.0V Voltage on VCC with respect to Ground ............. - 0.5V to 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA Injection Current at VCC = 0V to 5V(2) ....................... 5.0mA(1) Note: 1. Maximum current per port = 30mA 2. Functional corruption may occur. Table 29-1. Symbol VIL VIH VIH2 VOL VOH IILPORTA IIHPORTA IIHPORTB IILPORTB RRST Rpu DC Characteristics TA = -40C to 125C, VCC = 2.7V to 5.5V (unless otherwise noted)(1) Parameter Input Low Voltage Input High-voltage Except RESET pin Input High-voltage RESET pin Output Low Voltage(4) (Port B,PORTA) Output High-voltage(5) (Port B2:0,PORTA) Input Leakage Current I/O Pin Input Leakage Current I/O Pin Input Leakage Current I/O Pin Input Leakage Current I/O Pin Reset Pull-up Resistor I/O Pin Pull-up Resistor IOL = 10 mA, VCC = 5V IOL = 5 mA, VCC = 3V IOH = -10 mA, VCC = 5V IOH = -5 mA, VCC = 3V Vcc = 5.5V, pin low (absolute value) Vcc = 5.5V, pin high (absolute value) Vcc = 5.5V, pin low (absolute value) Vcc = 5.5V, pin high (absolute value) 30 20 <0.05 <0.05 4.3 2.5 50 50 1 1 60 50 Condition VCC = 2.4V - 5.5V VCC = 2.4V - 5.5V Min. -0.5 0.6VCC(3) 0.9VCC(3) Typ. Max. 0.3VCC VCC +0.5(2) VCC +0.5(2) 0.8 0.5 Units V V V V V V V nA nA A A k k 195 9151A-INDCO-07/09 Table 29-1. Symbol DC Characteristics TA = -40C to 125C, VCC = 2.7V to 5.5V (unless otherwise noted)(1) (Continued) Parameter Condition Active 1MHz, VCC = 3V Active 4MHz, VCC = 3V Power Supply Current Active 8MHz, VCC = 5V Idle 1MHz, VCC = 3V Min. Typ. 0.4 1.8 5.0 0.075 0.3 1.2 5.0 9.0 2.5 4.3 -50 Max. 1.5 3.0 10.0 0.2 0.5 2.5 30 50 24 36 50 Units mA mA mA mA mA mA A A A A nA ICC Idle 4MHz, VCC = 3V Idle 8MHz, VCC = 5V WDT enabled, VCC = 3V Power-down mode WDT enabled, VCC = 5V WDT disabled, VCC = 3V WDT disabled, VCC = 5V IACLK Notes: Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 1. All DC Characteristics contained in this data sheet are based on actual silicon characterization of ATtiny24/44/84 AVR microcontrollers manufactured in corner run process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual Automotive silicon. 2. "Max" means the highest value where the pin is guaranteed to be read as low. 3. "Min" means the lowest value where the pin is guaranteed to be read as high. 4. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 60 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 5. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Pull up driving strength of the PB3 RESET pad is weak. 29.2 Speed Grades Figure 29-1. Maximum Frequency vs. VCC 16MHz 8MHz Safe Operating Area 2.7V 4.5V 5.5V 196 ATA8742 9151A-INDCO-07/09 ATA8742 29.3 29.3.1 Clock Characterizations Calibrated Internal RC Oscillator Accuracy Calibration Accuracy of Internal RC Oscillator Frequency VCC 3V 2.7V - 5.5V 2.7V - 5.5V Temperature 25C -40C - 125C -40C - 125 Accuracy 2% 20% Standard Deviation 0.4 ns(1) Table 29-2. Factory Calibration User Calibration Oscillator Jitter Note: 8.0 MHz 7.3 - 8.1 MHz 8.0 MHz 1. The overall jitter increase proportionally to the divider ratio Example: with Oscillator divided by 32, jitter standard deviation will be 32 x 0.4 ns = 12.8 ns. 29.3.2 External Clock Drive Waveforms Figure 29-2. External Clock Drive Waveforms V IH1 V IL1 29.3.3 External Clock Drive Table 29-3. External Clock Drive VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. 0 50 20 20 1.6 1.6 2 0.5 0.5 2 Max. 20 Units MHz ns ns ns s s % Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Clock Frequency Clock Period High Time Low Time Rise Time Fall Time Change in period from one clock cycle to the next Min. 0 100 40 40 Max. 10 tCLCL 197 9151A-INDCO-07/09 29.4 System and Reset Characterizations Reset, Brown-out and Internal Voltage Reference Characteristics(1) Parameter Brown-out Detector Hysteresis RAM Retention Voltage (1) Table 29-4. Symbol VHYST VRAM2. tBOD VBG tBG IBG Notes: Condition Min Typ 100 Max 250 mV Units mV 50 2 VC C= 2.7V, TA = 25C VC C= 2.7V, TA = 25C VC C= 2.7V, TA = 25C 1.0 1.1 40 10 Min Pulse Width on Brown-out Reset Bandgap reference voltage Bandgap reference start-up time Bandgap reference current consumption ns 1.2 70 V s A 1. Values are guidelines only. 2. This is the limit to which VDD can be lowered without losing RAM data Table 29-5. BODLEVEL Fuse Coding(1) Min VBOT Typ VBOT Max VBOT Units BODLEVEL [2..0] Fuses 111 110 101 100 011 010 001 000 Note: BOD Disabled 1.8 2.7 4.3 2.3 2.2 1.9 2.0 V 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. 29.5 ADC Characteristics - Preliminary Data ADC Characteristics, Single Ended Channels. -40C - 125C Parameter Resolution Condition Single Ended Conversion Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Min Typ 10 Max Units Bits Table 29-6. Symbol 2.0 4.0 LSB TUE Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 2.0 4.0 LSB 198 ATA8742 9151A-INDCO-07/09 ATA8742 Table 29-6. Symbol ADC Characteristics, Single Ended Channels. -40C - 125C Parameter Integral Non-linearity (INL) Condition Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Free Running Conversion -5.0 Min Typ 0.5 Max 1.5 Units LSB INL DNL Differential Non-linearity (DNL) 0.3 0.7 LSB Gain Error -3.0 5.0 LSB Offset Error Conversion Time Clock Frequency Vref VIN VINT RAIN External Voltage Reference Input Voltage Internal Voltage Reference Analog Input Resistance -3.5 65 50 2.56 GND 1.0 1.5 3.5 260 200 AVCC VREF LSB s kHz V V V M 1.1 100 1.2 199 9151A-INDCO-07/09 Table 29-7. Symbol ADC Characteristics, Differential Channels, TA = -40C to 125C Parameter Resolution Gain = 20x Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 8 2.5 5.0 Bits LSB Condition Gain = 1x Min Typ 8 Max Units Bits TUE Absolute Accuracy Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 3.0 6.0 LSB 0.5 2.5 LSB INL Integral Non-Linearity (INL) Bipolar - Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Unipolar - Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 0.5 3.0 LSB 1.5 5.0 LSB 0.4 1.0 LSB DNL Differential Non-linearity (DNL) Bipolar - Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Unipolar - Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Bipolar -Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Unipolar -Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz -5.0 0.4 1.0 LSB 0.7 2.0 LSB 2.3 5.0 LSB -5.0 -2.8 5.0 LSB Gain Error Bipolar -Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Unipolar -Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz -7.0 2.2 7.0 LSB -7.0 -1.8 7.0 LSB 200 ATA8742 9151A-INDCO-07/09 ATA8742 Table 29-7. Symbol ADC Characteristics, Differential Channels, TA = -40C to 125C (Continued) Parameter Condition Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Offset Error Bipolar - Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Unipolar - Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz Clock Frequency Conversion Time Min -5.0 Typ 2.0 Max 5.0 Units LSB -5.0 2.0 5.0 LSB -6.5 50 65 2.56 GND -VREF/Gain 2.0 6.5 200 260 AVCC - 0.5 AVCC VREF/Gain LSB kHz s V V V VREF VIN VDIFF Reference Voltage Input Voltage Input Differential Voltage 29.6 Serial Programming Characteristics Figure 29-3. Serial Programming Timing MOSI tOVSH SCK MISO tSLIV Figure 29-4. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE tSHOX tSHSL tSLSH MSB LSB MSB LSB 201 9151A-INDCO-07/09 Table 29-8. Symbol 1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Note: Serial Programming Characteristics, TA = -40C to 125C, VCC = 2.7 - 5.5V (Unless Otherwise Noted) Parameter Oscillator Frequency (ATtiny24/44/84V) Oscillator Period (ATtiny24/44/84V) Oscillator Frequency (ATtiny24/44/84, VCC = 4.5V 5.5V) Oscillator Period (ATtiny24/44/84, VCC = 4.5V - 5.5V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid Min 0 250 0 50 2 tCLCL* 2 tCLCL* tCLCL 2 tCLCL TBD TBD TBD 20 Typ Max 4 Units MHz ns MHz ns ns ns ns ns ns 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz 29.7 High-voltage Serial Programming Characteristics Figure 29-5. High-voltage Serial Programming Timing CC CK Table 29-9. Symbol tSHSL tSLSH tIVSH tSHIX tSHOV tWLWH_PFB High-voltage Serial Programming Characteristics TA = 25C 10%, VCC = 5.0V 10% (Unless otherwise noted) Parameter SCI (PB0) Pulse Width High SCI (PB0) Pulse Width Low SDI (PA6), SII (PB1) Valid to SCI (PB0) High SDI (PA6), SII (PB1) Hold after SCI (PB0) High SCI (PB0) High to SDO (PA4) Valid Wait after Instr. 3 for Write Fuse Bits Min 110 110 50 50 16 2.5 Typ Max Units ns ns ns ns ns ms 202 ATA8742 9151A-INDCO-07/09 ATA8742 203 9151A-INDCO-07/09 30. Typical Characteristics - Preliminary Data The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 30.1 Active Supply Current Figure 30-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) - Temp.=25C ACTIVE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature = 25C 1.2 5.5 V 1 5.0 V 4.5 V 0.8 ICC (mA) 0.6 3.3 V 3.0 V 2.7 V 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-2. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) - Temp.=125C 204 ATA8742 9151A-INDCO-07/09 ATA8742 ACTIVE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature = 125C 1.2 1 5.5 V 5.0 V 0.8 ICC (mA) 4.5 V 0.6 0.4 3.3 V 3.0 V 2.7 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-3. Active Supply Current vs. frequency (1 - 20 MHz) - Temp.=25C ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 - 20 MHz - Temperature = 25C 25 20 ICC (mA) 15 10 5.5 V 5.0 V 4.5 V 3.3 V 3.0 V 2.7 V 5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-4. Active Supply Current vs. frequency (1 - 20 MHz) - Temp.=125C 205 9151A-INDCO-07/09 ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 - 20 MHz - Temperature = 125C 25 20 ICC (mA) 15 10 5.5 V 5.0 V 4.5 V 3.3 V 3.0 V 2.7 V 5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-5. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 8 MHz 7 6 5 ICC (mA) 125 85 25 -45 C C C C 4 3 2 1 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 206 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 30-6. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 1MHz 1.4 1.2 1 ICC (mA) 125 85 25 -40 C C C C 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 Figure 30-7. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE S UP P LY CURRENT vs . V CC INTERNAL RC OSCILLATOR, 128 KHz 0.2 0.16 ICC (mA) 0.12 -40 C 25 C 85 C 125 C 0.08 0.04 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 207 9151A-INDCO-07/09 30.2 Idle Supply Current Figure 30-8. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature 125C = 0.012 0.01 5.5 V 5.0 V 4.5 V 3.3 V 3.0 V 2.7 V 0.008 ICC (mA) 0.006 0.004 0.002 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-9. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE S UP P LY CURRENT vs . FREQUENCY 1 - 20 MHz - Temperature = 125 C 4 3.5 3 2.5 ICC (mA) 5.5 V 5.0 V 4.5 V 2 1.5 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 3.3 V 3.0 V 2.7 V 208 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 30-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 1.6 1.4 ICC (mA) 125 85 25 -40 C C C C 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 Figure 30-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 1 MHz 0.35 0.3 0.25 ICC (mA) 125 85 25 -40 C C C C 0.2 0.15 0.1 0.05 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 209 9151A-INDCO-07/09 Figure 30-12. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OSCILLATOR, 128 KHz 0.035 0.03 0.025 ICC (mA) 125 85 25 -40 C C C C 0.02 0.015 0.01 0.005 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 210 ATA8742 9151A-INDCO-07/09 ATA8742 30.3 Supply Current of IO modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "Power Reduction Register" on page 51 for details. Table 30-1. PRR bit Additional Current Consumption for the different I/O modules (absolute values) Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz 26 uA 35 uA 22 uA 87 uA VCC = 5V, F = 8MHz 106 uA 140 uA 87 uA 340 uA PRTIM1 PRTIM0 PRUSI PRADC 6.6 uA 8.7uA 5.5 uA 22 uA 211 9151A-INDCO-07/09 30.4 Power-down Supply Current Figure 30-13. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER DISABLED 5 4.5 4 3.5 ICC (uA) 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 V CC (V) 4.5 5 125 C 85 C 25 C -45 C 5.5 Figure 30-14. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER ENABLED 10 9 8 7 ICC (uA) 6 5 4 3 2 1 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 125 -45 85 25 C C C C 212 ATA8742 9151A-INDCO-07/09 ATA8742 30.5 Pin Pull-up Figure 30-15. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE V CC = 2.7V 90 80 70 60 IOP (uA) 50 40 30 20 10 0 0 0.5 1 1.5 V OP (V) 2 2.5 3 -45 25 85 125 C C C C Figure 30-16. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE V CC = 5.0V 160 140 120 100 IOP (uA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 V OP (V) 3 3.5 4 4.5 5 -45 25 85 125 C C C C 213 9151A-INDCO-07/09 Figure 30-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vc c = 2.7V 60 -40 C 50 125 C 40 IRE S E T (uA) 30 20 10 0 0 0.5 1 1.5 V RE S E T (V) 2 2.5 3 Figure 30-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vc c = 5.0V 120 -40 C 100 80 IRE S E T (uA) 125 C 60 40 20 0 0 0.5 1 1.5 2 2.5 V RE S E T (V) 3 3.5 4 4.5 5 214 ATA8742 9151A-INDCO-07/09 ATA8742 30.6 Pin Driver Strength Figure 30-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT LOW POWER PINS @ Vcc = 3V 0.06 125 C 0.05 0.04 V OL (V) 0.03 85 C 25 C -40 C 0.02 0.01 0 0 2 4 6 8 10 IOL (mA) 12 14 16 18 20 Figure 30-20. I/O pin Output Voltage vs. Sink Current (VCC = 5V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT LOW POWER PINS - Vcc = 5.0V 0.7 0.6 0.5 V OL (V) 125 C 85 C 25 C 0.4 -45 C 0.3 0.2 0.1 0 0 2 4 6 8 10 IOL (mA) 12 14 16 18 20 215 9151A-INDCO-07/09 Figure 30-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT LOW POWER PINS @ vcc = 3V 3.5 3 V OH (V) 2.5 -45 C 25 C 2 85 C 125 C 1.5 0 2 4 6 8 10 IOH (mA) 12 14 16 18 20 Figure 30-22. I/O Pin output Voltage vs. Source Current (VCC = 5V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT LOW POWER PINS @ vcc = 5V 5.1 5 4.9 4.8 V OH (V) 4.7 4.6 4.5 4.4 4.3 0 2 4 6 8 10 IOH (mA) 12 14 16 18 20 -45 C 25 C 85 C 125 C 216 ATA8742 9151A-INDCO-07/09 ATA8742 30.7 Pin Threshold and Hysteresis Figure 30-23. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as `1') I/O P IN INP UT THRES HOLD VOLTAGE vs . VC C VIH, IO PIN READ AS '1' 3.5 3 2.5 Thre s hold (V) 125 85 25 -40 C C C C 2 1.5 1 0.5 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 Figure 30-24. I/O Pin Input threshold Voltage vs. VCC (VIL, IO Pin Read as `0') I/O P IN INP UT THRES HOLD VOLTAGE vs . V C C VIL, IO PIN READ AS '0' 2.5 125 85 25 -40 C C C C 2 Thre s hold (V) 1.5 1 0.5 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 217 9151A-INDCO-07/09 Figure 30-25. I/O Pin Input Hysteresis vs. VCC I/O P IN INP UT HYS TERES IS vs . V CC 0.5 0.45 0.4 Input Hys te re s is (mV) 125 85 -20 -40 C C C C 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 Figure 30-26. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Threshold as `1') RES ET P IN AS I/O THRES HOLD VOLTAGE vs . VCC VIH, RESET READ AS '1' 3 2.5 125 85 25 -40 C C C C Thre s hold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 218 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 30-27. Reset Input Threshold Voltage vs. VCC (VIL, IO pin Read as `0') RES ET P IN AS I/O THRES HOLD VOLTAGE vs . V C C VIL, RESET READ AS '0' 3 2.5 Thre s hold (V) 2 125 85 25 -45 C C C C 1.5 1 0.5 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 Figure 30-28. Reset Pin Input Hysteresis vs. VCC RES ET P IN INP UT HYS TERES IS vs . V C C 1 0.9 0.8 Input Hys te re s is (mV) 0.7 0.6 0.5 0.4 0.3 0.2 -40 C 25 C 85 C 0.1 0 125 C 3 3.5 4 V CC (V) 4.5 5 5.5 2.5 219 9151A-INDCO-07/09 30.8 BOD Threshold and Analog Comparator Offset Figure 30-29. BOD Threshold vs. Temperature (BODLEVEL is 4.3V) BANDGAP VOLTAGE vs . TEMP ERATURE BOD = 4.3V 4.4 4.35 1 Thre s hold (V) 4.3 0 4.25 4.2 4.15 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (C) Figure 30-30. BOD Threshold vs, Temperature (BODLEVEL is 2.7V) BANDGAP VOLTAGE vs . TEMP ERATURE BOD = 2.7V 2.78 1 2.76 2.74 Thre s hold (V) 2.72 2.7 2.68 2.66 2.64 -40 0 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (C) 220 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 30-31. BOD Threshold vs. Temperature (BODLEVEL is 1.8V) BANDGAP VOLTAGE vs . TEMP ERATURE BOD = 1.8V 1.85 1.84 1 1.83 Thre s hold (V) 1.82 1.81 1.8 1.79 1.78 -40 0 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (C) 30.9 Internal Oscillator Speed Figure 30-32. Watchdog Oscillator Frequency vs. VCC WATCHDOG OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 124 122 120 118 FRC (kHz ) -40 C 116 114 112 110 108 106 104 2.5 25 C 85 C 125 C 3 3.5 4 V CC (V) 4.5 5 5.5 221 9151A-INDCO-07/09 Figure 30-33. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8.0MHz RC OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 9 8.5 8 FRC (MHz ) -40 25 85 125 C C C C 7.5 7 6.5 6 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 Figure 30-34. Calibrated 8 MHz RC oscillator Frequency vs. Temperature CALIBRATED 8.0MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.4 8.3 8.2 FRC (MHz ) 5.0 V 3.0 V 8.1 8 7.9 7.8 7.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature 222 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 30-35. Calibrated 8 MHz RC Oscillator Frequency vs, OSCCAL Value CALIBRATED 8.0MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE (Vcc=3V) 16 14 12 FRC (MHz ) 125 85 25 -40 C C C C 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 30.10 Current Consumption of Peripheral Units Figure 30-36. ADC Current vs. VCC ADC CURRENT vs . V C C 4.0 MHZ FREQUENCY 700 600 500 400 300 200 100 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 125 85 25 -40 C C C C ICC (uA) 223 9151A-INDCO-07/09 Figure 30-37. AREF External Reference Current vs. VCC AREF CURRENT vs . AREF VOLTAGE WHEN US ED AS ADC REFERENCE (Vc c =5.5V) 14 12 AREF pin c urre nt (uA) 25 C 10 8 6 4 2 0 1.5 2 2.5 3 3.5 AREF (V) 4 4.5 5 5.5 Figure 30-38. Analog Comparator Current vs. VCC ADC CURRENT vs . V C C 4.0 MHZ FREQUENCY 100 90 80 70 ICC (uA) -40 25 85 125 C C C C 60 50 40 30 20 10 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 224 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 30-39. Programming Current vs. VCC I/O MODULE CURRENT vs . VCC 4.0 MHZ FREQUENCY 12000 10000 25 C 8000 ICC (uA) 6000 4000 2000 0 2.5 3.5 V CC (V) 4.5 5.5 Figure 30-40. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs . VC C BOD level = 1.8V 16 14 12 10 ICC (uA) 125 C 8 6 4 25 C 85 C 2 -40 C 0 1.5 1.6 1.7 1.8 1.9 2 V CC (V) 2.1 2.2 2.3 2.4 2.5 225 9151A-INDCO-07/09 Figure 30-41. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs V C C 30 25 -40 25 85 125 C C C C 20 ICC (uA) 15 10 5 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 30.11 Current Consumption in Reset and Reset Pulse width Figure 30-42. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, excluding Current Through the Reset Pull-up) RES ET S UP P LY CURRENT vs . VC C EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.2 0.18 0.16 0.14 ICC (mA) 5.5 V 5.0 V 4.5 V 3.3 V 3.0 V 2.7 V 0.12 0.1 0.08 0.06 0.04 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 226 ATA8742 9151A-INDCO-07/09 ATA8742 Figure 30-43. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through the Reset Pull-up) RES ET S UP P LY CURRENT vs . V C C EXCLUDING CURRENT THROUGH THE RESET PULLUP 3 2.5 5.5 V 5.0 V 2 4.5 V ICC (mA) 1.5 1 3.6 3.3 3.0 2.7 V V V V 0.5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-44. Minimum Reset Pulse Width vs. VCC MINIMUM RES ET P ULS E WIDTH vs . V CC 1200 1000 Puls e width (ns ) 800 600 400 125 85 25 -40 C C C C 200 0 2.5 3 3.5 4 V CC (V) 4.5 5 5.5 227 9151A-INDCO-07/09 31. Register Summary Address 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31)) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name SREG SPH SPL OCR0B GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR0A TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL DWDR CLKPR ICR1H ICR1L GTCCR TCCR1C WDTCSR PCMSK1 EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB GPIOR2 GPIOR1 GPIOR0 PCMSK0 Reserved USIBR USIDR USISR USICR TIMSK1 TIFR1 Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved DIDR0 PRR Bit 7 I - SP7 - - - - - - FOC0A CAL7 COM0A1 COM1A1 ICNC1 Bit 6 T - SP6 INT0 INTF0 - - - PUD - FOC0B CAL6 COM0A0 COM1A0 ICES1 Bit 5 H - Bit 4 S - Bit 3 V - Bit 2 N - Bit 1 Z SP9 SP1 - - OCIE0A OCF0A PGERS ISC01 EXTRF CS01 CAL1 WGM01 WGM11 Bit 0 C SP8 SP0 - - TOIE0 TOV0 SPMEN ISC00 PORF CS00 CAL0 WGM00 WGM10 CS10 Page Page 24 Page 27 Page 27 Page 104 Page 69 Page 70 Page 105 Page 105 Page 178 Page 104 Page 69 Page 62 Page 103 Page 104 Page 48 Page 100 Page 129 Page 131 Page 133 Page 133 Page 133 Page 133 Page 133 Page 133 Page 174 SP5 SP4 SP3 SP2 Timer/Counter0 - Output Compare Register B PCIE1 PCIF1 - - - PCIE0 PCIF0 - - - - - - - - OCIE0B OCF0B CTPB RFLB PGWRT Timer/Counter0 - Output Compare Register A SM1 - - CAL4 COM0B0 COM1B0 WGM13 SM0 WDRF WGM02 CAL3 - - WGM12 CS12 - BORF CS02 CAL2 SE - - CAL5 COM0B1 COM1B1 - Timer/Counter0 CS11 Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Compare Register A High Byte Timer/Counter1 - Compare Register A Low Byte Timer/Counter1 - Compare Register B High Byte Timer/Counter1 - Compare Register B Low Byte DWDR[7:0] CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte TSM FOC1A WDIF - - EEAR7 - PORTA7 DDA7 PINA7 - - - - FOC1B WDIE - - EEAR6 - PORTA6 DDA6 PINA6 - - - - - WDP3 - - EEAR5 EEPM1 PORTA5 DDA5 PINA5 - - - - - WDCE - - EEAR4 EEPM0 PORTA4 DDA4 PINA4 - - - - - WDE PCINT11 - EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 - - WDP2 PCINT10 - EEAR2 EEMPE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 - - WDP1 PCINT9 - EEAR1 EEPE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PSR10 - WDP0 PCINT8 EEAR8 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 Page 48 Page 134 Page 134 Page 137 Page 132 Page 62 Page 70 Page 38 Page 38 Page 38 Page 38 Page 87 Page 87 Page 87 Page 87 Page 87 Page 88 Page 40 Page 40 Page 40 EEPROM Data Register General Purpose I/O Register 2 General Purpose I/O Register 1 General Purpose I/O Register 0 PCINT7 PCINT6 PCINT5 PCINT4 - USI Buffer Register USI Data Register USISIF USISIE - - USIOIF USIOIE - - USIPF USIWM1 ICIE1 ICF1 USIDC USIWM0 - - - - ACD REFS1 ADEN ACBG REFS0 ADSC ACO MUX5 ADATE ACI MUX4 ADIF ACIE MUX3 ADIE ACIC MUX2 ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 USICNT3 USICS1 - - USICNT2 USICS0 OCIE1B OCF1B USICNT1 USICLK OCIE1A OCF1A USICNT0 USITC TOIE1 TOV1 PCINT3 PCINT2 PCINT1 PCINT0 Page 71 Page 146 Page 146 Page 146 Page 147 Page 134 Page 135 Page 152 Page 166 Page 169 Page 170 Page 170 ADC Data Register High Byte ADC Data Register Low Byte BIN ADC7D - ACME ADC6D - - ADC5D - ADLAR - ADC4D - ADC3D PRTIM1 ADC2D PRTIM0 ADC1D PRUSI ADC0D PRADC - ADTS2 ADTS1 ADTS0 Page 171 Page 153,Page 172 Page 51 228 ATA8742 9151A-INDCO-07/09 ATA8742 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 229 9151A-INDCO-07/09 32. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers Description Rd Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF -Rd Rd 0x00 -Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd -1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd -Rr Rd -Rr -C Rd -K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC+k + 1 if (SREG(s) = 0) then PC PC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 BRANCH INSTRUCTIONS BIT AND BIT-TEST INSTRUCTIONS 230 ATA8742 9151A-INDCO-07/09 ATA8742 Mnemonics ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (z) R1:R0 Rd P P Rr STACK Rr Rd STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 2 2 1 1 1 N/A 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 Operands Rd Rd Rd Rd s s Rr, b Rd, b Description Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Operation Rd(0) C,Rd(n+1)Rd(n),C Rd(7) Rd(7) C,Rd(n)Rd(n+1),C Rd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C 1 C 0 N 1 N 0 Z 1 Z 0 I 1 I 0 S 1 S 0 V 1 V 0 T 1 T 0 H 1 H 0 Flags Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H #Clocks 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MCU CONTROL INSTRUCTIONS 231 9151A-INDCO-07/09 Appendix 2: Appendix B - ATA8743/ATA8741/ATA8742 Automotive Specification at 1.8V 232 ATA8742 9151A-INDCO-07/09 ATA8742 33. Description This document contains information specific to devices operating at voltage between 1.8V and 3.6V. Only deviations with standard operating characteristics are covered in this appendix, all other information can be found in the complete Automotive datasheet. The complete ATtiny24/ATtiny44/ATtiny84 automotive datasheet can be found on www.atmel.com. 233 9151A-INDCO-07/09 34. Electrical Characteristics 34.1 Absolute Maximum Ratings Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Operating temperature Storage temperature Voltage on any pin except RESET with respect to ground Maximum operating voltage DC current per I/O pin DC current VCC and GND pins Value -40 to +85 -65 to +175 -0.5 to VCC + 0.5 6.0 30.0 200.0 Unit C C V V mA mA 34.2 DC Characteristics Parameters Condition Min. -0.5 0.7VCC(2) -0.5 0.9VCC -0.5 0.9VCC (2) (2) TA = -40C to +85C, VCC = 1.8V to 3.6V (unless otherwise noted) Symbol VIL VIH VIL1 VIH1 VIL2 VIH2 VOL VOH Typ. Max. +0.2VCC(1) VCC + 0.5 +0.2VCC(1) VCC + 0.5 +0.2VCC (1) Unit V V V V V V V V Input low voltage, except XTAL1 and VCC = 1.8V to 3.6V RESET pin Input high voltage, except XTAL1 and RESET pins Input low voltage, XTAL1 pin Input high voltage, XTAL1 pin Input low voltage, RESET pin Input high voltage, RESET pin Output low voltage(3), I/O pin except RESET Output high voltage(4), I/O pin except RESET Power supply current VCC = 1.8V to 3.6V VCC = 1.8V to 3.6V VCC = 1.8V to 3.6V VCC = 1.8V to 3.6V VCC = 1.8V to 3.6V IOL = 2 mA, VCC = 1.8V IOH = -2mA, VCC = 1.8V Active 4 MHz, VCC = 3V Idle 4 MHz, VCC = 3V WDT disabled, VCC = 3V WDT enabled, VCC = 3V VCC = 2.7V Vin = VCC/2 VCC = 2.7V Vin = VCC/2 VCC + 0.5 0.2 1.2 0.8 0.2 0.2 4 < 10 -50 2.5 0.5 24 30 40 +50 mA mA A mV nA ICC Power-down mode VACIO IACLK Notes: Analog comparator Input offset voltage Analog comparator Input leakage current 1. "Max" means the highest value where the pin is guaranteed to be read as low 2. "Min" means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (2 mA at VCC = 1.8V) under steady state conditions (nontransient), the following must be observed: (1) The sum of all IOL, for all ports, should not exceed 50 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (0.5 mA at VCC = 1.8V) under steady state conditions (nontransient), the following must be observed: (1) The sum of all IOL, for ports B0 to B5, should not exceed 50 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 234 ATA8742 9151A-INDCO-07/09 ATA8742 34.3 Maximum Speed versus VCC Maximum frequency is dependent on VCC. As shown in Figure 34-1, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 3.6V. Figure 34-1. Maximum Frequency versus VCC 8 MHz 4 MHz Safe Operating Area 1.8V 2.7V 3.6V 34.4 Clock Characterizations Calibration Accuracy of Internal RC Oscillator Frequency VCC 1.8V to 3.6V Temperature -40C to +85C Accuracy 25% 7.3 MHz to 8.1 MHz Table 34-1. User Calibration 235 9151A-INDCO-07/09 34.5 ADC Characteristics Parameters Resolution Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) Test Conditions Single ended conversion VCC = 1.8V, VRef = 1.8V, ADC clock = 200 kHz VCC = 1.8V, VRef = 1.8V, ADC clock = 200 kHz Noise Reduction Mode VCC = 1.8V, VRef = 1.8V, ADC clock = 200 kHz VCC = 1.8V, VRef = 1.8V, ADC clock = 200 kHz VCC = 1.8V, VRef = 1.8V, ADC clock = 200 kHz VCC = 1.8V, VRef = 1.8V, ADC clock = 200 kHz -7.0 -3.5 1.8 Min. Typ. 10 2 4.0 Max. Unit Bits LSB TA = -40C to +85C, VCC = 1.8V to 3.6V (unless otherwise noted) Symbol 2 4.0 LSB Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain error Offset error VREF Reference voltage 0.5 0.2 -3.0 +1.5 1.5 0.7 +5.0 +3.5 AVCC LSB LSB LSB LSB V 34.6 ADC Characteristics Parameters Resolution Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) Integral Non-Linearity (INL) Test Conditions Differential conversion, gain = 1x BIPOLAR mode only Gain = 1x, VCC = 1.8V, VRef = 1.3V, ADC clock = 125 kHz Gain = 1x, VCC = 1.8V, VRef = 1.3V, ADC clock = 125kHz Gain = 1x, VCC = 1.8V, VRef = 1.3V, ADC clock = 125 kHz Gain = 1x, VCC = 1.8V, VRef = 1.3V, ADC clock = 125 kHz Gain = 1x, VCC = 1.8V. VRef = 1.3V, ADC clock = 125 kHz -7.0 Min. Typ. 8 Max. Unit Bits TA = -40C to +85C, VCC = 1.8V to 3.6V (unless otherwise noted) Symbol 1.6 5.0 LSB 0.7 2.5 LSB Differential Non-Linearity (DNL) 0.3 1.0 LSB Gain Error +1.50 +7.0 LSB Offset Error -4.0 0.0 +4.0 AVCC - 0.5 LSB VREF Reference Voltage 1.30 V 236 ATA8742 9151A-INDCO-07/09 ATA8742 35. Ordering Information Extended Type Number ATA8742-PXQW Package QFN24 5 mm x 5 mm Remarks Microcontroller with UHF Tx for 429 MHZ to 439 MHz 36. Package Information Package: QFN 24 - 5 x 5 Exposed pad 3.6 x 3.6 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm Not indicated tolerances 0.05 0.90.1 0.05-0.05 24 1 0.4 18 19 +0 5 3.6 24 1 technical drawings according to DIN specifications 6 0.3 13 12 7 6 0.65 nom. Drawing-No.: 6.543-5122.01-4 Issue: 1; 15.11.05 3.25 237 9151A-INDCO-07/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support industrial@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2009 Atmel Corporation. All rights reserved. Atmel(R), Atmel logo and combinations thereof, AVR (R), AVR(R) Studio and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 9151A-INDCO-07/09 |
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